Lab 106 (AI KIT): RADAR Sensor

The BGT60TR13C is a 60 GHz Frequency Modulated Continuous Wave (FMCW) radar sensor featuring an antenna-in-package with one transmitter (Tx) and three receivers (Rx). It includes an integrated Finite State Machine (FSM) that enables independent data acquisition with optimized power modes. Unlike the I2C sensors on this kit, the radar communicates with the PSoC 6 MCU via a high-speed SPI interface (up to 50 MHz)
using pins P12.3 (CS), P12.2 (CLK), P12.0 (MOSI), and P12.1 (MISO), along with an interrupt pin P11.0 (IRQ).

After applying power, the sensor enters a Deep Sleep state once the internal LDO settles. To prepare the device for configuration:

1. Enable the internal clock: Write 1 to the OSCCLKEN bit in the PACR1 register (0x04) to enable the 80 MHz system clock path.
2. Wait for components to settle: Allow the required time for the ADC bandgap and main Phase-Locked Loop (PLL) to initialize.
3. Enable the Data Header (Optional but recommended): Write 1 to the PREFIX_EN bit in the SFCTL register (0x06). This adds a synchronization header (starting with a 0x000000 sync-word) prior to the raw chirp data in the FIFO, making it much easier for the host MCU to parse frames and avoid corrupted data.

Radar operation is based on defining specific modulation sequences called "shapes" (e.g., Upchirp, Downchirp, Saw-tooth) which are grouped into "frames".

1. Define Frequency Shapes: Program the PLLx (e.g., PLL1_0 to PLL1_7) registers to set the frequency sweep properties. You must define the start frequencies (FSU/FSD), ramp step sizes (RSU/RSD), ramp times (RTU/RTD), and the number of ADC samples per chirp (APU/APD).
2. Define the Frame Structure: Program the Chirp Control Registers (CCR0, CCR1, CCR2) to determine how many shape groups make up a frame, how many frames to execute, and the time delays between them.
3. Set Power Modes: Configure the power states the FSM should drop into between chirps or frames to save power. You can define transitions between Active, Interchirp, Idle, and Deep Sleep modes using the channel set control registers (CSCx) and chirp control registers.

Once the FSM is fully configured with your desired shapes and frames:

1. Write 1 to the FRAME_START bit (bit 0) in the MAIN register (0x00).
2. The FSM will now take over and automatically generate the RF chirps, sample the analog baseband via the ADCs, and push the digitized 12-bit data into the internal FIFO.

The digitized radar data is stored in a large full-duplex FIFO buffer (8192 words x 24 bits).

1. Wait for the Interrupt: Wait for the RSPI_IRQ pin (P11.0) to trigger, indicating that the FIFO has reached the programmed comparison reference level (FIFO_CREF).
2. Initiate a Burst Read: Because of the large amount of data generated by the radar, you must use the SPI Burst Mode Command to read from the FIFO continuously without addressing each register.
3. Send the following 32-bit burst command to read an undefined number of sampling data from the FIFO address (0x60): ADDR = 0x7F, RW = 0x01, SADDR = 0x60, RWB = 0x0, NBURSTS = 0x00.
4. Capture the 24-bit data words continuously. If PREFIX_EN was enabled in Step 1, use the 0x000000 sync-word to align your data array and separate the X, Y, and Z receiver samples.