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MIPS CPU (Verilog FPGA)
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EE4480-Lab 01: Integer Multiplication Hardware
EE4480-Lab 02: Integer Division Hardware
EE4480-Lab 03: Single-Cycle MIPS Datapath
EE4480-Lab 04: Single-Cycle MIPS Control
EE4480-Lab 05: Multi-Cycle MIPS Data Path
EE4480-Lab 06: Multi-Cycle MIPS Control
EE4480-Lab 07: Pipelined MIPS Datapath
EE4480-Lab 08: Pipelined MIPS Control
EE4480-Lab 09: Pipelined MIPS Data Hazard
EE4480-Lab 10: Pipelined MIPS Branch Hazard - Predic Not Taken
EE4480-Lab 11: Pipelined MIPS Branch Hazard - Static Prediction
EE4480-Lab 12: Pipelined MIPS Branch Hazard - Dynamic 1bit Prediction
EE4480-Lab 13: Pipelined MIPS Branch Hazard - Dynamic 2bit Prediction
EE4480-Lab 14: Floating-Point Processor
EE4480-Lab 15: Exceptions
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