Lesson 02: Verilog HDL


Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a language used to describe electronic systems and digital logic circuits. For example, a computer or a component of a computer. One may describe a digital system at several levels. For example, an HDL might describe the layout of the wires, resistors, and transistors on an Integrated Circuit (IC) chip, i. e., the switch level. Or, it might describe the logic gates and flip-flops in a digital system, i. e., the gate level. An even higher level describes the registers and the transfers of vectors of information between registers. This is called the Register Transfer Level (RTL). Verilog supports all of these levels. However, this course focuses on only the portions of Verilog which support the RTL level.

Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL was developed under a contract from DARPA. Many people feel that Verilog is easier to learn and use than VHDL. The main reason is that Verilog is very similar to C and most electrical and computer engineers learn C in college, so Verilog HDL is more popular with them.

Table 1: Verilog and VHDL Compared

Parameters of ComparisonVerilogVHDL
Introduced in 1984 in 1980
Data Type Weakly typed Strongly typed
Language Looks like C Looks like Ads (Pascal)
Alphabets Case sensitive Case insensitive
Syntax Terse Verbose
Developer Design by a few Design by committee
Area of Use Used all over Mandated by government
Difficulty of Learning Easy to learn Harder to learn
Larger and Complex circuit Easy to screw up Holds your hand closely

Identifiers are names given to modules, variables, and other elements of the language so that they can be referenced in the design. In the Verilog, identifiers have the following characteristics:

  • It can be composed of letters (a ~ z, A ~ Z), numeric characters (0 ~ 9), and underscore (_).
  • Must start with an alphabetic character or an underscore, not with a number.
  • Identifiers are case-sensitive.
  • It cannot be the same as Verilog keywords.