Lesson 03: Variables and Data Types

All variables in Verilog have a predefined type. There are only two families of data types: nets and registers.

  • Net variables act like wires in a physical circuit and establish connectivity between design objects representing hardware units.
  • Register variables act like variables in computer programming languages — they store information while the program executes.

 

 

  • The Left Hand Side (LHS) of procedural assignments must be of a Register type.
  • For continuous assignments outside of procedural blocks, LHS must be Nets (wires)

 

 

 

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