Lesson 01: Create a New FPGA Project using Quartus Prime Standard

Creating a Project

You can create a new project by clicking New Quartus Prime Project on the File ➤ New... menu. When creating a new project, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity. You can also specify which design files, other source files, user libraries, and EDA tools you want to use in the project, as well as the target device.

1. Launch Quartus (Quartus Prime 21.x) Lite (or Standard) Edition
   There should be a desktop icon. Otherwise, search through the Windows Start menu to find it.
   
2. Start the New Project Wizard
   In the Quartus Prime window, click on the menu File ➤ New...,  select on Quartus Prime Project, then click on the OK button.
   
3. Next, the Introduction page opens. Click on the Next button.
   
4. Select the Working Directory, Project Name, and Top-Level Design Entity Name
   In the next screen, enter a directory in which you will store your Quartus Prime project files for this design, for example, R:\Project\EE4480\MyFirstFPGA\MyFirstFPGA.
   Enter the project name, type MyFirstFPGA.
   Enter the name of the top-level design entity for this project. By default, this name is the same as the project name. Here, I would recommend adding "_top" at the end of the name, so you can easy to recognize which file is the top-level module file. Here, you can type MyFirstFPGA_top.
   Click Next.
   
   
   Note: A window may pop up stating that the chosen working directory does not exist. Click Yes to create it.
            
   
   
   Don't use any space or special characters in the file, and project names. Use an underscore ( _ ) if you need to put a space in your file or project name.
5. Next, you have to select the project type. Please select the Empty project, then click on the Next button.
   
6. In the next dialog, click Next again as we will not be adding any preexisting design files at this time.
   
7. Select the Family and Device Settings
   Select the family and device you used for this project, then click on the Next button.
   
   • From the pull-down menu labeled Device family, select MAX 10(DA/DF/DC/SA/SC).
   • In the list of available devices:
     • If you are using terasIC DE10-Lite Board, please select 10M50DAF484C7G device.
     • If you are using Arrow BeMicro MAX 10 Evaluation Kit Board, please select 10M08DAF484C8GES device.
   • Click Next
   
   
8. Select simulation tool:
   • For 20.1 or newer versions:
     In the EDA Tool Settings dialog, select Simulation to Questa Intel FPGA, and Format(s) to Verilog HDL. Then click Next.
     
   • For 20.0.1 or previous version:
     In the EDA Tool Settings dialog, select Simulation Tool Name to ModelSim-Altera, and Format(s) to Verilog HDL. Then click Next.
     
9. Finally, the New Project Wizard will show you a summary of this project. Click Finish to complete the New Project Wizard.
   

Create Top-Level Design and 2-to-1 MUX

After creating the project file, the next step is going to the design entry phase. In this phase, you create a Verilog HDL File (.v) that is the top-level design.

In Quartus, the top-level module must have the same name as the top-level design entity name you entered in the New Project Wizard window and must be in a file with the same name and a ".v" extension.

1. To create the top-level module goes back to the main Quartus Prime window:
   Select File ➤ New... from the Menu bar.
   Select Verilog HDL File, from the Design Files list and click OK. 
   
2. After clicking OK, a new empty file will automatically open. You can type your Verilog code in Quartus Text Editor.
   
3. Copy and paste the following code into your new Verilog file, then save it by selecting File ➤ Save. Keep the default file name and click Save in the Save As dialog box.
   

   module MyFirstFPGA_top(SW, LEDR);
       input   [9:0] SW;
       output  [9:0]  LEDR;
   
       assign in0 = SW[0];
       assign in1 = SW[1];
       assign sel = SW[2];
       assign LEDR[0] = out;
       mux_2to1 mux21(.in0(in0), .in1(in1), .sel(sel), .out(out));
   
   endmodule

4. Save the Verilog file. By default, the file name of the first Verilog file in the project will be the same as the top-level name, which you entered when creating a new project.

After creating top-level module files, the next step is going to the design sub-module — 2-to1 MUX.

1. Select File ➤ New... from the Menu Bar.
   Select Verilog HDL File from the Design Files list and click OK.
   
2. Copy and paste the following code into your new Verilog file, then save it by selecting File ➤ Save. Change the filename to mux_2to1.v and click Save.
   

   module mux_2to1(in0, in1, sel, out);
       input  in0, in1, sel;
       output out;
   
       wire nsel;
       wire a0, a1;
   
       not not1(nsel, sel);
       and and1(a0, in0, nsel);
       and and2(a1, in1, sel);
       or  or1 (out, a0, a1);
   endmodule

Compile the Design and Check the RTL Viewer

Compile your Verilog code.

1. Save all open files, and then partially compile the design by clicking the Processing ➤ Start Compilation ➤ Start Analysis & Elaboration. or click the  icon.
   
    
2. This will take a few minutes. You can check the progress (%), which is at the bottom right of the screen. Once it stopped (progress to 100%), please look for any errors being displayed in the message box. If there were errors, try to fix them and try again. You may ignore any warnings that may appear at this time.
   
    
3. After you perform a successful Analysis & Elaboration, you can view the design in the RTL Viewer, and you can view the hierarchy in the Project Navigator window. The Quartus RTL Viewer provides graphical representations of your design. To display the RTL Viewer, on the Tools menu, point to Netlist Viewers, and then click RTL Viewer.

Create a Test Bench File

For this tutorial, the code that we want to test is a simple 2-to-1 multiplexor circuit. We will be running a simulation on the computer to test the logic, to make sure there are no mistakes. This is faster than compiling and uploading to the FPGA board, and it is very powerful to be able to test the circuit without actually having to test it on hardware yet.

1. Create a new file by going File ➤ New... ➤ Verilog HDL File, and click OK.
   
2. Next, we will write the testbench code as shown below. Save the filename as "test_tb.v" file.
   

   `timescale 1ns/1ps
   
   module test_tb;
   
   reg in0, in1, sel;
   wire out;
   wire [9:0] SW, LEDR;
   
   MyFirstFPGA_top DUT(SW, LEDR);
   
   assign SW[0] = in0;
   assign SW[1] = in1;
   assign SW[2] = sel;
   
   assign out = LEDR[0];
   
   initial begin
               sel = 0; in1 = 0; in0 = 0;
       #10     sel = 0; in1 = 0; in0 = 1;
       #10     sel = 0; in1 = 1; in0 = 0;
       #10     sel = 0; in1 = 1; in0 = 1;
       #10     sel = 1; in1 = 0; in0 = 0;
       #10     sel = 1; in1 = 0; in0 = 1;
       #10     sel = 1; in1 = 1; in0 = 0;
       #10     sel = 1; in1 = 1; in0 = 1;
       #10     $stop;
   end
   
   endmodule

   Note: The testbench module does not contain any inputs or outputs, and it instantiates an instance of our mux module that we want to test calling it "DUT".

3. Once you have finished writing everything, including the testbench, and everything compiles correctly, you can move to the next step.

Config Questa-Intel FPGA Simulation

Next, we need to set up the Simulation for the project.

1. Click Assignments ➤ Settings ➤ EDA Tool Setting ➤ Simulation.
   
   On the Simulation page, specify the following values for the options:
   
   • Tool name: Questa Intel FPGA
   • Run gate-level simulation automatically after compilation: unchecked
   • Format for output netlist: Verilog HDL
   • (2) Under NativeLink settings, select the Compile testbench option
   • (3) Click the Test Benches... button
2. On the Test Benches page, click the New option to create a new test bench.
   
3. Specify test_tb as the Test bench name, and test_tb as the Top-level module in test bench.
   Check the Use test bench to perform VHDL timing simulation and DUT as the Design instance name in test bench.
   Under Test bench and simulation files, enter or select the test_tb.v file, click Add, and click OK.
   
4. The Test Benches dialog box displays the properties of the test benches in your project.
   
5. Click OK to exit Test Benches and Settings dialogs.

Launch Simulation

To generate and run Questa-Intel FPGA Edition automation script from within the Intel Quartus Prime Standard Edition software, follow these steps:

1. Click Processing ➤ Start Compilation or click the icon to compile the design and generate the .do file. The Messages window indicates when compilation is complete.
   
   
2. If there is no error, then click Tools ➤ Run Simulation Tool ➤ RTL Simulation. The Intel Quartus Prime Standard Edition software launches the Questa-Intel FPGA Edition simulator and simulates the test_tb.v file, according to your specifications in the Simulation settings.
   
3. On the Questa window, click the Wave panel. The simulation waveform ends at 80ns, as the testbench specifies. The Wave panel lists the in0, in1, sell, and out signals.
4. If you got any problems, close Questa, fix the problems, and then run the Start Compilation again.

Assign Pins

The DE10-Lite board has hardwired connections between the FPGA chip and onboard switches, seven-segment displays, and lights. To use those components, it is necessary to include in your Quartus project the correct pin assignments, which are given in your board’s user manual (Lesson KB 02: Intel DE10-Lite Board). For example, the DE10-Lite manual specifies that SW[0] is connected to the FPGA pin C10 and LEDR[0] is connected to pin A8. A good way to make the required pin assignments is to import into the Quartus software the pin assignment file for your board, which can be downloaded from here: DE10_Lite.qsf. Please download the QSF file and save it under your lab folder.

Importing Pin Assignments

With a project opened in Quartus, importing pin assignments are very simple. The detailed steps are as shown below.

1. First, download DE10_Lite.qsf file.
2. From the Menu Bar, select Assignments ➤ Import Assignments...
   
3. Click ellipses next to Filename in the Import Assignments window that popped up.
   Locate the file DE10_Lite.qsf, select the checkbox for the Copy existing assignment into <project>_top.qsf.bak before importing.
   Then click the Advanced... button.
   
4. In the Advanced Import Settings window, check the Global assignments, then click OK.
   
5. Click OK again to import DE10_Lite.qsf into your project.
6. Check the Pin Assignment
   From the Menu Bar, select Assignment ➤ Assignment Editor. A complete list of pin assignments for the DE10-Lite board will be shown on the screen.
   
7. Viewing Pin Assignments with the Pin Planner
   To access the Pin Planner either click on the Pin Planner Icon, use the shortcut CTRL+SHIFT+N, or select the Pin Planner from the Assignments menu of the Quartus toolbar.
   
8. Recompile the design by clicking Processing ➤ Start Compilation.

Program the FPGA board

You must install the Altera USB-Blaster or Altera USB-Blaster II driver before you can use it to program devices with Quartus Prime software.

The following shows how the FPGA is programmed in JTAG mode step by step.

1. On the DE10-Lite board, plug the USB cable into the USB Blaster Port. Plug the other end of the USB cable into the computer.
2. In the Quartus Prime window, click the Programmer button  on the Toolbar, or select Tools ➤ Programmer from the Menu Bar to open the Programmer window.
   
3. The Hardware Setup... must be USB-Blaster [USB-xx]. If not, click the Hardware Setup... button and select USB-Blaster [USB-0] from the drop-down menu for Currently selected hardware. The mode should be set to JTAG. Click Close to close the window.
   
4. If you can see an FPGA device on the Programmer screen, you can skip this step. Otherwise, click Auto Detect to detect all the devices on the JTAG chain, and select detected device associated with the board to 10M50DA. Click OK to detect the devices.
   
5. Right-click on the FPGA device and click Change File to open the .sof file to be programmed.
   
6. Click Program/Configure check box, and then click the Start button to download the .sof file into the FPGA device.
   

When the progress bar reaches 100%, programming is complete.

You can now test the program on the DE10-Lite board by using the slide switches located along the bottom of the board.

• SW0 is the one bit of data for input0.
• SW1 is the one bit of data for input1.
• SW2 is the selector input to the multiplexer.
• The output of the multiplexer is displayed on the first green LED located above the slide switches on the DE10-Lite board.