KB 02: DE10-Lite Board

The DE10-Lite development board includes board-specific status LEDs to indicate board status as shown as below.

Figure 2: Status LED Position

Table 1: Status LED

The DE10-Lite board has a 24 MHz oscillator, which is connected to a clock generator, CDCE937. The clock generator is used to distribute clock signals with low jitter and provides the following clock signals to the FPGA board:

• The two 50 MHz clock signals connected to the FPGA are used as clock sources for user logic.
• One 24 MHz clock signal is connected to the clock inputs of the USB microcontroller of USB Blaster.
• One 10 MHz clock signal is connected to the PLL1 and PLL3 of FPGA. The outputs of these two PLLs can drive the ADC clock.

Figure 3: Clock Circuit of the MAX10-Lite Board

Table 2: Pin Assignment of Clock Inputs

Do not modify the clock generator settings. The incorrect setting will cause the system to not work.

The DE10-Lite board includes two user-defined push buttons that allow users to interact with the MAX 10 FPGA. Each of these switches is connected as negative logic input with pull-up resistors on the board, as shown in Figure 4.

Figure 4: Connection between the Push-Button and MAX 10 FPGA

Table 3: Pin Assignment of Push-Buttons

There are ten slide switches connected to FPGA on the board. These switches are used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to a pin on the MAX 10 FPGA.

• When the switch is in the DOWN position (closest to the edge of the board), it provides a low logic level to the FPGA.
• When the switch is in the UP position, it provides a high logic level.

Figure 5: Connections between the slide switches and MAX 10 FPGA

Table 4: Pin Assignment of Slide Switches

There are ten user-controllable LEDs connected to FPGA on the board. Each LED is driven directly and individually by a pin on the MAX 10 FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off (Positive Logic Outputs).

Figure 6: Connections between the LEDs and MAX 10 FPGA

Table 5: Pin Assignment of LEDs

The DE10-Lite board has six 7-segment displays to display numbers. Each seven-segment display consists of seven LED bars, and a single LED round for the decimal point. The DE10-Lite board uses the common anode (CA) method for its displays. This means that all the anodes are tied together and connected to the power source. The segment can be turned ON or OFF by applying a low logic level or high level from the FPGA, respectively (Negative Logic Output). Figure 6 shows the connection of seven segments to pins on MAX 10 FPGA.

Figure 7: Connections between the 7-Segment Display HEX0 and the MAX 10 FPGA

Table 6: Pin Assignment of 7-Segment Displays

The DE10-Lite board has one 40-pin expansion header. Each header has 36 user pins connected directly to MAX 10 FPGA. It also comes DV +5V (VCC5), DC+3.3V (VCC3P3), and two GND pins. Both 5V and 3.3V can provide a total of 5W power.

Figure 8: I/O Distribution of the Expansion Headers

Table 7: Pin Assignment of Expansion Headers

The DE10-Lite board also provides an Arduino Uno revision 3 compatibility expansion header, which comes with four independent headers. The expansion header has 17 user pins: included 16 pin2 GPIO and 1 pin Reset) connected directly to the MAX 10 FPGA. 6-pin Analog input connects to ADC and provides DC +5V (VCC5), DC +3.3V (VCC3P3 and IOREF), and three GND pins.

Figure 9: Pin Out Signals Name of the Arduino Uno Connector. (The Blue Font Represents the Arduino Pin-Out Definition)

The MAX 10 FPGA has two ADC channels: ADC1 and ADC2. On the DE10-Lite board, only ADC1 is brought out to pins, and there is no access to ADC2 inputs. The ADC configurations on MAX 10 FPGA are shown as below:

• 2 ADC channels
• SAR type conversion
• 12-bit conversion
• 1MHz (max) operation
• 1 dedicated input/channel
• 8 programmable inputs/channel
• 0 ~ 2.5V conversion range Arduino analog pins (A0 ~ A5) are mapped to ADC1IN1 ~ ADC1IN6.

The DE10-Lite board has eight analog inputs that are connected to MAX 10 FPGA ADC1 through a 1x6 and a 1x2 header input, wherein the 1x2 header is reserved and not mounted with parts.

All analog input signals that are sourced through the Arduino header JP8 are first filtered by the Analog Front-End circuit. This circuit scales the maximum allowable voltage per the Arduino specification (5.0V) to the maximum allowable voltage per the MAX 10 FPGA ADC IP block (2.5V).

Figure 10: The Analog Front-End Circuit between the Arduino Analog Input and MAX 10 FPGA

The 12-bit of ADC value represents 0 ~ 2.5V input voltage to the ADC hardware. In the ADC front-end circuit, the output voltage is half of the input voltage. So the input voltage to the Arduino analog input can be calculated with the formula listed below:

\[Vol {_{input}} = {{AD{C_{12 - bit}}} \over {4096}} \times 2.5 \times 2 = {{AD{C_{12 - bit}}} \over {4096}} \times 5\quad (V)\]

Table 10: Pin Assignment of ADC

The DE10-Lite board includes a 15-pin D-SUB connector for VGA output. The VGA synchronization signals are provided directly from the MAX 10 FPGA, and a 4-bit DAC using resistor-network is used to produce the analog data signals (red, green, and blue). The associated schematic is given in Figure 11 and can support standard VGA resolution (640x480 pixels, at 25 MHz).

Figure 11: Connections Between the VGA and MAX 10 FPGA

Table 11: Pin Assignment of VGA

The board features 64MB of SDRAM with a single 64MB (32Mx16) SDRAM chip. The chip consists of a 16-bit data line, control line, and address line connected to the FPGA. This chip uses the 3.3V LVCMOS signaling standard. Connections

Figure 12: Connections between the SDRAM and MAX 10 FPGA

Table 12: Pin Assignment of SDRAM

The board comes with a digital accelerometer sensor module (ADXL345), commonly known as G-sensor. This G-sensor is a small, thin, ultralow-power assumption 3-axis accelerometer with high-resolution measurement. Digitalized output is formatted as 16-bit in two’s complement and can be accessed through SPI (3- and 4-wire) and I2C digital interfaces.

Figure 13: The Connections between the Accelerometer Sensor and MAX 10 FPGA.

Table 13: Pin Assignment of Accelerometer Sensor

I2C Mode

I2C Mode

If the CS pin is tied high to V_DD (logic 1), the ADXL345 will operate in I2C slave mode. The I2C address is configured by the GSENSOR_SDO pin, and the address values are shown below.

 

Signal Name	Setting	Description
GSENSOR_SDI	I2C DAT	I2C Serial Data
GSENSOR_SDO	Address	0: I2C Address = 0x53 1: I2C Address = 0x1D
GSENSOR_CS_N	1	I2C Mode
GSENSOR_SCLK	I2C CLK	I2C Clock

 

SPI (4-Wire) Mode

SPI (3-Wire) Mode

The DE10-Lite board supports the dual image boot function. If you want to use this function, you will need to solder the JP5 with a 2-pin header (pitch 0.1" = 0.25mm) by yourself.

Figure 14: JP5 Position on the DE10-List Board.

Table 14: JP5 Jumper Setting Instructions