FPGA Lab 05: Binary Adder/Subtractor, and Decimal Adder



  •  Design of 4-bit adder/subtractor using hierarchical gate-level modeling


Required Reading Material

  • Textbook: Digital Design: with An Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th edition, Mano and Ciletti, ISBN-13: 978-0-13-454989-7
    Ch 4.5

Background Information

You will to first learn how to run the Quartus Prime synthesis tool to compiler your hardware design to a file that can be downloaded and run on the FPGA. Work through this Lesson 01: Create a New FPGA Project using Quartus Prime Standard to learn how this is done. You will be doing this compilation many times during the rest of the labs, so you might as well take your time and understand how it works.

Designing with Verilog

In this lab, you will convert schematics into Verilog modules to build a relatively complex design. Verilog is a hardware description language. Although it may look like a programing language, Verilog is used to describe the functionality of the hardware. Verilog programs are not actually executed by hardware like C or Java programs; instead, they are turned into the hardware circuit described by Verilog code. Your design will be comprised of several modules that will be connected together using structural modeling in Quartus.