Lesson 08: Dataflow Modeling

Gate-level modeling is useful for writing Verilog code for small designs. However, it may be cumbersome to use gate-level modeling for writing Verilog code for large designs. Dataflow modeling can be used for describing the behavior of large circuits. This type of modeling utilizes Boolean operators along with logical expressions. Hence, dataflow modeling in Verilog allows a digital system to be designed in terms of its function.

Dataflow modeling utilizes Boolean equations and uses a number of operators that can act on inputs to produce outputs. There are approximately 30 Verilog operators. These operators can be used to synthesize digital circuits. Some of the operators are listed in the Lesson 04-Operators session.

Dataflow modeling uses continuous assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a net. The datatype net is used in Verilog HDL to represent a physical connection between circuit elements. The value assigned to the net is specified by an expression that uses operands and operators. As an example, assuming that the variables were declared, a 2-to-1 multiplexer with data inputs A nad B, select input S, and output Y is described with a continuous assignment:

assign Y = (A & S) | (B & S);