Infineon (Cypress) PSoC 5LP Labs
PSoC Creator
PSoC 5LP Lab + RobotSoC Kit
Platform:
- PSoC 5LP Embedded Board (EagleSoC Board / CY8CKIT-059 Prototyping Board)
- PSoC Creator 4.4
- RobotSoC Starter Kit
Before you begin the lab, please read the following requirements.
- Lab 01: Switch and LED Control without C Code
- Lab 02: Switch and LED Control with C Code
- Lab 03: UART-Based LED Control and Switch State Monitoring
- Lab 04: Ultrasonic Module HC-SR04
- Lab 05: Thermometer
- Lab 06: Passive and Active Buzzers
- Lab 07: Analog Joystick Module
- Lab 08: PWM DC Motor and Servo Control
- Lab 09: I2C RTC Module
- Lab 10: 7-Segment Display Modules
- Lab 11: Stepper Motor
- Lab 12: DHT11/22, RHT03 Temperature and Humidity Sensor (1-Wire)
- Lab 13: Tilt Ball Switch, Passive and Active Buzzer
- Lab 14: Walking Man on MAX7219 LED Dot Matrix Module
- Lab 15: Matrix Keypad
- Lab 16: Rotary Encoder Module
- Lab 17: MPU6050 IMU Sensor
- Lab 18: RC-522 RFID Module
- Lab 19: Water Level Detection Sensor Module
- Lab 20: Sound Sensor Module
- Lab 21: CapSense
- Lab 22: Digital Filter
- Lab23: Building a UART‑Based Single‑Application Bootloader
FreeRTOS
FreeRTOS on PSoC 5LP — Lab Series Master Index
Platform:
- PSoC 5LP Embedded Board (EagleSoC Board / CY8CKIT-059 Prototyping Board)
- PSoC Creator 4.4
- FreeRTOS Kernel V11
- RobotSoC Starter Kit
Technical arc (5 phases)
Phase 1 — Foundations (01-05): what an RTOS buys over a superloop, kernel integration on PSoC 5LP, task lifecycle and control, preemptive scheduling and time slicing, drift-free periodic timing.
- Lab 01: Bare-Metal Superloop vs. RTOS
- Lab 02: FreeRTOS Kernel Integration
- Lab 03: Task Control: Suspend
- Lab 04: Preemptive Scheduling, Starvation & Time Slicing
- Lab 05: Periodic Tasks & Timing Accuracy
Phase 2 — Synchronization & IPC (06–11): task notifications, queues, binary/counting semaphores, mutex and priority inversion, event groups, software timers — the full inter-task toolkit.
- Lab 06: Direct-to-Task Notification
- Lab 07: Queues: Producer / Consumer
- Lab 08: Binary & Counting Semaphores
- Lab 09: Mutex & Priority Inversion
- Lab 10: Event Groups & System Coordination
- Lab 11: FreeRTOS Software Timers
Phase 3 — Interrupts & Memory (12–13): the deferred-interrupt pattern and the NVIC syscall safety line; heap/stack/fault visibility and the safety hooks.
Phase 4 — Applied Integration (14–18): real subsystems — a UART command interface, filtered ADC monitoring, PWM control, shared I2C/SPI bus management — then one integrated system guarded by a watchdog.
- Lab 14: UART Command Interface
- Lab 15: ADC Monitoring & Filtering
- Lab 16: PWM Control
- Lab 17: I2C / SPI Resource Management
- Lab 18: Integrated Application + Wat
Phase 5 — Systems Engineering (19–27): production concerns — low-power/tickless idle, multi-task synchronization patterns, waiting on many sources, fully static (no-heap) builds for determinism, observability/debugging, critical sections / the mutual-exclusion toolbox, DMA-offloaded bulk I/O, schedulability analysis (RMA / WCET / RTA), and fault handling (HardFault diagnosis & recovery) as the last net in defense-in-depth.
- Lab 19: Low-Power & Tickless Idle
- Lab 20: Task Synchronization Patterns
- Lab 21: Waiting on Many Sources: Queue Sets & Advanced Notifications
- Lab 22: Fully Static FreeRTOS (No Heap)
- Lab 23: Observability & Debugging
- Lab 24: Critical Sections & Mutual Exclusion
- Lab 25: DMA + RTOS
- Lab 26: Schedulability Analysis (RMA, WCET & Response-Time Analysis)
- Lab 27: Fault Handling (HardFault Diagnosis & Recovery)
Technique & API reference
| Lab | Key techniques | Core APIs |
|---|---|---|
| 01 | Superloop limits; task vs superloop; the scheduler; first two tasks | xTaskCreate, vTaskStartScheduler, vTaskDelay |
| 02 | FreeRTOS_Init() builds the vector table; RTOS_USED; boot order; SVC/PendSV/SysTick | FreeRTOS_Init, CyGlobalIntEnable, vTaskStartScheduler |
| 03 | Task states; suspend/resume; self-suspend; scheduler suspend; delete | vTaskSuspend, vTaskResume, vTaskSuspendAll, vTaskDelete |
| 04 | Preemption; priorities; starvation; configUSE_TIME_SLICING 0 vs 1; yield | uxTaskPriorityGet/Set, taskYIELD, configUSE_TIME_SLICING |
| 05 | vTaskDelay drift vs xTaskDelayUntil absolute grid; seed xLastWakeTime once | xTaskDelayUntil, xTaskGetTickCount, pdMS_TO_TICKS |
| 06 | Notification as a fast binary signal; ISR → task deferral | vTaskNotifyGiveFromISR, ulTaskNotifyTake, portYIELD_FROM_ISR |
| 07 | By-value queue; producer/consumer decoupling; full/empty/timeout, back-pressure | xQueueCreate, xQueueSend, xQueueReceive |
| 08 | Binary vs counting semaphore; the drain pattern; give from ISR | xSemaphoreCreateBinary/...Counting, xSemaphoreGiveFromISR, xSemaphoreTake |
| 09 | Mutex; priority inversion → inheritance; lock ordering / deadlock | xSemaphoreCreateMutex, xSemaphoreTake, xSemaphoreGive |
| 10 | Event bits AND/OR; clear-on-exit; multi-condition coordination | xEventGroupCreate, xEventGroupSetBits, xEventGroupWaitBits |
| 11 | One-shot vs auto-reload; xTimerReset inactivity; callback must not block; daemon task | xTimerCreate, xTimerStart/Reset/Stop, xTimerChangePeriod |
| 12 | Deferred interrupt; two priority systems; NVIC 2–7 safety line; (2<<5); masking | vTaskNotifyGiveFromISR, portYIELD_FROM_ISR, isr_*_SetPriority |
| 13 | heap_4 coalescing; free / min-ever heap; stack high-water; the two hooks; static vs dynamic | xPortGetFreeHeapSize, xPortGetMinimumEverFreeHeapSize, uxTaskGetStackHighWaterMark, vApplicationStackOverflowHook, vApplicationMallocFailedHook |
| 14 | Stream buffer (bytes) + queue (commands); trigger level; line parse; two-stage pipeline | xStreamBufferSendFromISR, xStreamBufferReceive, xQueueSend |
| 15 | Periodic sampling grid; moving average vs IIR/EWMA; hysteresis / deadband | xTaskDelayUntil, xQueueSend/Receive |
| 16 | Hardware vs software PWM; slew-rate limiting / fade; double-buffered compare; setpoint via queue | PWM_WriteCompare, xTaskDelayUntil, xQueueReceive |
| 17 | Shared-bus atomic transaction; mutex + priority inheritance; bus-server alternative | xSemaphoreCreateMutex, xSemaphoreTake, xSemaphoreGive |
| 18 | System integration; hardware watchdog; health heartbeats + supervisor; reset reason | CyWdtStart, CyWdtClear, CyResetStatus / CY_RESET_WD |
| 19 | xTaskDelayUntil vs suspend; tickless idle; deep-sleep hooks; energy = duty cycle | configUSE_TICKLESS_IDLE, CyPmSaveClocks/CyPmSleep/CyPmRestoreClocks, vTaskStepTick, configPRE/POST_SLEEP_PROCESSING |
| 20 | Rendezvous; barrier (xEventGroupSync); gatekeeper; why not suspend/resume for sync | xEventGroupSync, xTaskNotifyGive/Wait, xQueueSend/Receive |
| 21 | Queue sets; notification as bits / counter / mailbox; indexed notifications | xQueueCreateSet, xQueueAddToSet, xQueueSelectFromSet, xTaskNotify, xTaskNotifyWait |
| 22 | Static allocation; kernel-memory callbacks; no-heap build; .map RAM budget | xTaskCreateStatic, xQueueCreateStatic, vApplicationGetIdleTaskMemory, vApplicationGetTimerTaskMemory, configSUPPORT_DYNAMIC_ALLOCATION |
| 23 | Trace facility; run-time stats (CPU %); live dashboard; configASSERT + tripwires | uxTaskGetSystemState, vTaskList, vTaskGetRunTimeStats, configASSERT |
| 24 | Critical sections; _FROM_ISR forms; suspend-all vs mutex; torn access; the latency cost | taskENTER_CRITICAL/taskEXIT_CRITICAL, taskENTER_CRITICAL_FROM_ISR/..._EXIT_..., vTaskSuspendAll, xTaskResumeAll |
| 25 | DMAC channel + TD; arm → block → notify → process; double-buffering (ping-pong); offload bulk I/O | <DMA>_DmaInitialize, CyDmaTdAllocate, CyDmaTdSetConfiguration, CyDmaChEnable; vTaskNotifyGiveFromISR, ulTaskNotifyTake |
| 26 | Periodic task model (T,C,D,U); WCET measurement; Rate-Monotonic; utilisation bound; response-time analysis; blocking term | xTaskDelayUntil; run-time stats (Lab 23) for C; RM priority assignment; RTA iteration |
| 27 | Cortex-M3 fault family & escalation; recover the stacked frame (MSP/PSP); decode HFSR/CFSR/BFAR; post-mortem over UART; reset vs graceful degradation; defence in depth | CyIntSetSysVector, HardFault_Handler (naked asm stub), SCB->HFSR/CFSR/BFAR/SHCSR, CySoftwareReset, CyResetStatus |