Verilog FPGA

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Lesson 00: General Requirements for FPGA Laboratories
Lesson 01: Create a New FPGA Project using Quartus Prime Standard
Lesson 02: Verilog HDL
Lesson 03: Data Types
Lesson 04: Verilog Scalar, Vector, and Array
Lesson 05: Expressions, Operands, and Operators
Lesson 06: Modules and Ports
Lesson 07: Gate-Level (Structural) Modeling
Lesson 08: Dataflow Modeling
Lesson 09: Behavioral Modeling
Lesson 10: Tasks, Functions, and Directives
Lesson 11: Testbench
Lesson 12: Run Simulation on ModelSim (Pre-Simulation)
Lesson 13: State Machines
Lesson 14: Memories in Verilog
Lesson KB 01: Install Intel Quartus Prime Lite and Driver
Lesson KB 02: Intel DE10-Lite Board
Lesson KB 03: Intel FPGA M9K Embedded Memory Blocks
Lesson KB 04: Verilog FAQ
Lesson KB 05: Synthesizable Coding of Verilog