Lesson 06: Modules and Ports
Verilog describes a digital system as a set of modules. A module is the main building block in Verilog which contains the statements specifying the circuit and it can be compared to functions() in C language. Modules can be embedded within other modules, and a higher-level module can connect with its lower-level modules using their input and output ports.
Modules
A typical Verilog segment is given below:
module <module name> (<port list>);
<port declarations>
<module declarations>
<module items>
endmodule
In Verilog, a module is declared by the keyword module and a corresponding keyword endmodule must appear at the end of the module definition. Each module must have a unique module name, which is the identifier for the module, and a port list, which describes the input and output terminals of the module. An entire circuit can be described in a module.
Module Name
module name
The module name identifies a module uniquely. This means that a name or an identifier is assigned to a module to identify it.
Port List and Declarations
Port list
The port list of a module is the interface between the module and its environment. The port list is enclosed in parentheses, and commas are used to separate elements of the list. The statement is terminated with a semicolon (;)
port declarations
All the ports that are in the port list, need to be declared as input, output, or inout (for bidirectional signals). The direction of the port can be specified in either the port list or the port declarations, but cannot be both.
Declare the direction of ports in the port declaration (Verilog-1995)
module mux4to1( in0, in1, in2, in3, sel, out);
input in0, in1, in2, in3;
input [1:0] sel;
output out;
endmodule
Declare the direction of the ports inside the port list (Verilog-2001, 2005)
module mux4to1( input in0, input in1, input in2, input in3, input sel[1:0], output out);
// No port declarations are needed
endmodule
module mux2to1( input in0, in1, sel, output out);
// No port declarations are needed
endmodule
Verilog File
The first step to design a digital circuit using Verilog is to draw a module diagram, as shown below. In the module diagram, the following items must be declared:
- Name of module
- Type of its connections (input, output, or bidirectional signal)
- Names of each port
Then, write the Verilog code for the module. Usually, a Verilog source file contains only one module, and the module name should match the Verilog source file name.
Figure 1: Draw a Module Diagram
module01.v
module module01 (a, b, c, x, y, z);
input [3:0] a;
input b;
input c;
output [7:0] x;
output y;
inout z;
endmodule
However, multiple modules can reside in a Verilog file, but external modules can connect to a module matching the Verilog file name, and other modules can only be connected inside the Verilog file, so this is not recommended.
Figure 2: Multiple Modules in one Verilog File
mainMod.v
module mainMod (a, b, c, z);
input a, b, c;
output [3:0] z;
endmodule
module subMod(x, y,z):
input x, y;
output z;
endmodule
Top-Level Module
A top-level module is one that contains all other modules. A top-level module is not instantiated within any other module.
For example, design modules are normally instantiated within top-level testbench modules so that simulation can be run by providing input stimulus. But, the testbench is not instantiated within any other module because it is a block that encapsulates everything else and hence is the top-level module.