FPGA Lab 05: Binary Adder/Subtractor, and Decimal Adder
- Design of 4-bit adder/subtractor using hierarchical gate-level modeling
Required Reading Material
- Textbook: Digital Design: with An Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th edition, Mano and Ciletti, ISBN-13: 978-0-13-454989-7
You will to first learn how to run the Quartus Prime synthesis tool to compiler your hardware design to a file that can be downloaded and run on the FPGA. Work through this Lesson 01: Create a New FPGA Project using Quartus Prime Standard to learn how this is done. You will be doing this compilation many times during the rest of the labs, so you might as well take your time and understand how it works.
Designing with Verilog
In this lab, you will convert schematics into Verilog modules to build a relatively complex design. Verilog is a hardware description language. Although it may look like a programing language, Verilog is used to describe the functionality of the hardware. Verilog programs are not actually executed by hardware like C or Java programs; instead, they are turned into the hardware circuit described by Verilog code. Your design will be comprised of several modules that will be connected together using structural modeling in Quartus.
1-bit Full-Adder Design
A 1-bit full-adder has three binary inputs and two binary outputs:
Two of the inputs are the two significant bits to be added of number a and number b. And the third input cin (Carry-In) is the carry from the previous lower significant position.
The two outputs are the sum and cout (Carry-out).
$[cout, sum] = cin = a + b$
Fill in the truth table for the full-adder listed in Table 1.1 with the formula $[cout,s] = cin + a + b$. Then, using K-maps to simplify the Boolean equations for output cout and sum. Write down your final equations in SOP or POS format.
Table 1.1: Full-Adder
K-Map for cout
K-Map for sum
The Circuit of a 1-bit Full-Adder
According to the Boolean expressions, draw the circuit of the sum and cout by using logical gates: AND, OR, XOR, and NOT gates in schematic 01. And also define all connection wires with a unique net name.