Lesson 02: ARM Cortex-M Instruction Set

Floating-point Instructions (Cortex-M4)

The Cortex-M4 processor comes with an FPU co-processor. It provides floating-point computation functionality compliant with the ANSI/IEEE std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.

The FPU supports all single-precision data-processing instructions: add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats and floating-point constant instructions.

FPU Register Bank

The FPU provides an extension register file containing 32 single-precision registers.

• Sixteen 64-bit double-word registers, D0 ~ D15
• Thirty-two 32-bit single-word registers, S0 ~ S31

The FPU register bank is shown in the following diagram:

You can access the Least-Significant half of the value in D6 by accessing S12 and the Most-Significant half of the elements by accessing S13.

Enabling the FPU

The FPU is disabled from reset. You must enable it before you can use any floating-point instructions. Example 4.1 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must be in privileged mode to read from and write to the CPACR.

; CPACR is located at address 0xE000ED88
        LDR.W   R0, =0xE000ED88
; Read CPACR
        LDR     R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
        ORR     R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
        STR     R1, [R0]; wait for store to complete
        DSB
;reset pipeline now the FPU is enabled
        ISB

ARM Cortex-M Instruction Groups