Lesson 03: Data Types

All variables in Verilog have a predefined type. There are only two families of data types: nets and registers.

  • Net variables act like wires in a physical circuit and establish connectivity between design objects that represent hardware units.
  • Register variables act like variables in computer programming languages — they store information while the program executes.

 

 

Logic Values

Verilog supports four logic values and eight strengths to model the functionality of real hardware. There are two additional unknown logic values that may occur internal to the simulation but cannot be used for modeling.

Logic ValueDescription
0 Zero, Low, or False
1 One, High, or True
x or X Unknown, Don't care, or Uninitialized (either 0 or 1)
z or Z Undefined, High-Impedance, or Floating
L Partially unknown; either 0 or Z, but not 1 (Internal simulation value only)
H Partially unknown; either 1 or Z, but not 0 (Internal simulation value only)

 

 

Verilog has two major data type classes:

  • Net data types are used to make connections between parts of a design.
    • Nets reflect the value and strength level of the drivers of the net or the capacitance of the net and do not have a value of their own.
    • Nets have a resolution function, which resolves a final value when there are multiple drivers on the net.
  • Variable data types are used as temporary storage of programming data.
    • Variables can only be assigned a value from within an initial procedure, an always procedure, a task, or a function.
    • Variables can only store logic values; they cannot store logic strength.
    • Variables are un-initialized at the start of the simulation and contain a logic x until a value is assigned.

 

 

  • The Left Hand Side (LHS) of procedural assignments must be of a Register type.
  • For continuous assignments outside of procedural blocks, LHS must be Nets (wires)