Lab 05: Boolean Algebra and Verilog Simulation

Boolean Algebra is a mathematical approach to deriving equivalent functions. It is desirable to be able to simplify a function in order to design a circuit that uses fewer gates which can result in a more compact, lower-power design or to reduce the propagation delay of a signal through the circuit in order to speed up the circuit.

The table below shows the various identities that can be used to simplify a function.

Table 5.1.1: Boolean Algebra Identities

The easiest to derive a form of the function is the canonical representation, either Sum of Minterms or Product of Maxterms. A minterm is a product term that contains every input variable and a maxterm is a sum term that contains every input variable. Minterm i will evaluate to true (1) for input combination i. Maxterm i will evaluate to false (0) for input combination i. The table below shows the minterms (products) and maxterms (sums) for all possible input combinations for a 3-variable function with input variables A, B, and C.

Table 5.1.2: Minterm and Maxterm

A function can easily be expressed using a Sum of Minterms expression by taking the logical sum (OR) of the function's minterms (ANDs); i.e., for every input combination that produces a one at the output. Likewise, a function can easily be expressed using a Product of Maxterms expression by taking the logical product (AND) of the function's Maxterms (ORs); i.e., for every input combination that produces a zero at the output.

Consider the XOR and XNOR functions shown in this table.

Table 5.1.3: Truth Table of XOR and XNOR

The exclusive-oR of A and B, A ⊕ B, can be expressed as the sum of minterms 1 and 2. That is,

A ⊕ B = m1 + m2 = Σm(1, 2) = A B + A B

The exclusive-nor of A and B, (A ⊕ B) can be expressed as the sum of minterms 0 and 3. That is,

(A ⊕ B) = m0 + m3 = Σm(0, 3) = A B + A B

The exclusive-or of A and B, A ⊕ B, can be expressed as the products of Maxterms 0 and 3. That is,

A ⊕ B = M0 • M3 = ΠM(0, 3) = (A + B)(A + B)

The exclusive-nor of A and B, (A ⊕ B) can be expressed as the product of Maxterms 1 and 2. That is,

(A ⊕ B) = M1 • M2 = ΠM(1, 2) = (A + B)(A + B)

Question

1. In this part of the experiment you should do the following (in your lab report):
   • Explore three different functions for implementing the majority voter, V, described in Lab 4. The first, referred to as F1, is the function for V from Lab 4: F1 = AB + BC + AC.
   • Write the truth table for the majority voter, V, with inputs A, B, and C (this was derived in Lab 4).
   • Express V using the sum of minterms notation. Call this function F2.
   • Express V using the product of maxterms notation. Call this function F3.
   • Use the Boolean Algebra Identities (see Table 5.1) to prove that F1 = F2. Show the steps and label each step with the appropriate identity/Law.
     Hint, you can use the Idempotent law to add additional redundant minterms.
   • Use the Boolean Algebra Identities to prove that F1 = F3. Show the steps and label each step with the appropriate identity/Law.

In this part of the experiment, you will verify the Consensus Theorem (A B + A C + B C = A B + A C) by implementing the following two functions using the Verilog Hardware Description Language (HDL), simulating the Verilog functions using the online simulator, and verifying that they both produce the same simulation waveform. (That F1 = F2 can also be verified by drawing a K-map for each.)

F1 = A B + A C + B C

F2 = A B + A C

The purpose of this experiment is to help you learn the basics of designing combinational logic circuits using a hardware description language (HDL), to learn the basics of how to model a circuit using gate-level modeling in Verilog, and how to verify that a circuit works properly using a simulator.

Follow along with the instructions provided to implement F1 and F2 in Verilog and simulate the circuits to verify that F1 is equivalent to F2. Record notes and observations in your manual to assist you in the future when designing circuits in Verilog.

ModelSim

Download ModelSim - Intel FPGA Edition (Includes Starter Edition) from https://fpgasoftware.intel.com/.

When you install ModelSim, the system will ask you to choose which edition you want to install. Since we do not need the license for this lab experiment, select ModelSim - IntelFPGA Starter Edition, and click Next >. Then, follow the setup instructions to install the ModelSim on your computer.

Figure 5.1: Install ModelSim-Intel FPGA Starter Edition, which License is not Required

After you install ModelSim, follow the steps to create a Verilog in ModelSim.

1. Launch the  ModelSim - Intel FPGA Starter Edition from the Windows Start button. 
2. Please read the FPGA-Lesson 12: Run Simulation on ModelSim (Pre-Simulation) and follow the instructions to learn how to create a project in ModelSim. Record your observations in your manual to assist you to create a new project for this assignment.
3. On your Windows desktop, create a new folder for this lab experiment, and name it "EE2449_Lab05". Then, create a new project in ModelSim, and name it concensus.
4. Add new Verilog files into the project
   • concensus.v
   • concensus_tb.v

///////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Data:    09:30:00 08/12/2020
// Design Name:
// Module Name:    concensus
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////

module concensus( A, B, C, F1, F2);
input A, B, C;
output F1, F2;

endmodule

///////////////////////////////////////////////////////////////////////////////
// Company:   EE-2449 Digital Logic Lab
// Engineer:  you and your partner's name
//
// Create Data:    09:30:00 08/12/2020
// Design Name:    Lab 05
// Module Name:    concensus_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns

module concensus_tb;
    reg     A, B, C;    // Input
    wire    F1, F2;     // Output

  // Instantiate the Unit Under Test (UUT)
    concensus UUT( .A(A), .B(B), .C(C), .F1(F1), .F2(F2));

    initial begin
        // Display the results
        $monitor("time=%02d: ABC = %b%b%b  F1 = %b, F2 = %b \n",$time,  A, B, C, F1, F2 );

        // Initialize Inputs
            A = 0; B = 0; C = 0;

        // Wait for 100 ns for the global reset to finish
        #100;

        // Add stimulus here

        #20 $stop;
    end
endmodule

5. Save the files and compile the code to ensure that there are no syntax errors, then run the simulation in ModelSim.
6. Before running the testbench code, add A, B, C, F1, and F2 signals to the Wave window. Then click Simulate ➤ Run ➤ Run-All to execute the simulation. 
7. You should see the results in the Wave window as shown below:
   
   
   Figure 5.4: The Results in the Wave Window

In the waveform, note that starting at 100 ns, the values of ABC count from 000 to 111 and at 180 ns got back to 000. Reading the simulation waveform is similar to reading the oscilloscope waveforms except in this case we can see all inputs and outputs together. This is a very useful function and in fact, there are logical analyzers that are similar to oscilloscopes that capture and display multiple inputs and outputs in digital hardware design.

Note that F1 and F2 have the same waveform which proves that they are the same function. If you do not obtain the correct results, there must be an error in your design that you need to fix. In this example, if your results do not show that F1 and F2 are the same, there is an error in your design in the consensus module. Go back and fix it and repeat the steps to simulate the code.

Show your instructor your code and simulation results. Also, print out and paste the code and simulation results into your lab report.

Questions

2. Describe intuitively why the term BC is redundant in F1.
   Hint: Consider the other two terms AB and AC and the possible values of A. (Example: if A = 1, then F1 = BC + B. Is BC still needed?)

Fill the boolean results for F1 = AB + BC + AC into the following truth table:

Table 5.3.1: Truth Table for F1 Boolean Expression

Use ModelSim to implement the three functions for the majority voter in Verilog and run the simulation to verify that the three functions are the same.

F1 = AB + BC + AC

F2 = Sum of Minterms (determined in Exp #5.1 based on the Table 5.3.1)

F3 = Product of Maxterms (determined in Exp #5.1 based on the Table 5.3.1).

Follow the process outlined in Exp #5.2 to design your circuit in Verilog using gate-level modeling and to simulate your design. Show your instructor your code and simulation results. Also, print out and paste the code and simulation results into your lab report.

Questions

3. What is the benefit of designing (and simulating) a circuit in a hardware description language (HDL) such as Verilog before building it in hardware?