# PSoC Lab 03: Using Verilog Code to Create Components for PSoC 5LP

## Background Information

Cypress PSoC 5LP is not just a microcontroller. It integrates the functions of a microcontroller, complex programmable logic device (CPLD), and high-performance analog components. The goal of this lab is to introduce and teach how to create your own Verilog-based components using PSoC Creator. You will step through the given example project to design two shift right counters using different modeling methods; one that shift counter using Gate-level (Structrue) modeling method to do it, and one that using Behavior modeling only on the shift right counter. After that, you will write Verilog-code to create two 4-bit shift left counter components using the same methods as the example project.

### Shift Right Counter

Shift counters are a type of sequential logic circuit. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. All flip-flop is driven by a common clock, and all are set or reset simultaneously.

A basic four-bit shift right counter can be constructed using four D flip-flops, as shown in Figure 1.

Figure 1: Shift-Right 4-bit Counter

The operation and design specs of the circuit are as follows.

1. 4-bit synchronous shift right counter.
2. The counter is first cleared, forcing all four output to zero.
3. The input data is then applied sequentially to the d input of the first flip-flop on the left (FF3).

## Required Components List

 Push Button x 1 Resistor: 220 ohm x 4 Red LED x 4

## Procedure

#### Create Verilog Component: Shift Right Counter

Now, let us design a Verilog-based shift right counter with synchronous reset using the PSoC Creator.

#### 4-bit Shift Right Component Creating Steps

You can use an existing project and add a new component to it, but for this lab, use an empty project as a starting point.

1. Launch PSoC Creator 3.x and start a new project.
• In the dialog under Design Project, select Target Device and choose the device you are using, and then click Next.
• The chip on the CY8CKIT-059 is CY8C5888LTI-LP097
• The chip on the EagleSoC Board is CY8C5888AXI-LP096
• The Chip on the EagleSoC Mini Board is CY8C5888LTI-LP097
• On the next screen, select Empty Schematic and click Next.
• On the final screen, change the Workspace and Project name to EE446, and Verilog01_ShiftRight, and click Finish.
2. In the Components tab of the Workspace Explorer panel, right-click on the "Verilog01_ShiftRight" project and then click Add Component Item form the context menu.
It is good practice to include a version number in the component name. Append to the component name the tag '_vX_YY', where 'X' is the major version and 'YY' us the minor version.
3. Select Symbol Wizard component template and name the component 'ShiftRight_v1_00'.

Figure 2: Creating a Custom Component

4. To launch the component symbol wizard, click the Create New button.
This wizard asks you to define the inputs and outputs, and it uses this information to create a component symbol.
5. Define two digital input terminals, one clock input terminal, and one 4-bit digital output terminal for the schematic symbol as shown in Figure 3.

Figure 3: Symbol Creation Wizard for Shift Right

Click OK to generate the symbol in the symbol schematic, as shown in Figure 4.

Figure 4: Initial Symbol for Shift Right

You can resize the component, and modify the appearance of the component, as shown in Figure 5.

Figure 5: Shift Right Final Symbolm

6. Right-click on an empty space in the symbol schematic, and the click Properties. In the Symbol section of the property fields, click on the ellipsis (...) on Doc.CaralogPlacement, as shown in Figure 6.

Figure 6: Symbol Properties Dialog Box

7. Enter EE446/Digital/Shift Right 4-bit in the Catalog Placement dialog, as shown in Figure 7.
This places the Shift in the EE446 tab of the Component Catalog window, under the 'Digital' sub-folder, with the catalog name of 'Shift Right 4-bit'.

Figure 7: Setting Catalog Placement

The next step is to link the schematic symbol to a Verilog file. PSoC Creator generates a Verilog shell based on the component symbol.

8. To do this, right-click on empty space in the symbol schematic and then click Generate Verilog. Retain the default settings in the Generate Verilog dialog box and click Generate, as shown in Figure 8.

Figure 8. Generate the Verilog File for the Symbol

The Target values can be used to limit the configuration to a specific device, but for this lab use the default setting.
A Verilog file for the symbol just created appears.

Note: There are three #start - #end pairs in the Verilog file. When editing the file, put you code within these sections. Changes made to Verilog file outside these sections will be lost if you regenerate the Verilog file.

You are now ready to describe the Shift Right in Verilog.

#### First Verilog Design: 4-bit Shift Right Counter (Using D Flip-Flops)

There are three modeling methods to design the Verilog code: Gate-level modeling, Dataflow modeling and Behavior modeling.

In the first design, we create a D flip-flop module using behavior modeling, and then connect four D flip-flops using Gate-level modeling in the ShiftRight module.

The Verilog code as below:

//#start header -- edit after this line, do not edit this line
// ========================================
//
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
include "cypress.v"
//#end -- edit above this line, do not edit this line
// Generated on 01/31/2016 at 22:44
// Component: ShiftRight_v1_00
module ShiftRight_v1_00 (
output [3:0] q,
input   clk,
input   d,
input   reset
);

//#start body -- edit after this line, do not edit this line

D_FF dff0(d,    clk, reset, q[0]);
D_FF dff1(q[0], clk, reset, q[1]);
D_FF dff2(q[1], clk, reset, q[2]);
D_FF dff3(q[2], clk, reset, q[3]);
//#end -- edit above this line, do not edit this line
endmodule
//#start footer -- edit after this line, do not edit this line
module D_FF(d, clk, reset, q);
input  d;
input  clk, reset;
output reg q;

always @(negedge clk or posedge reset) begin
if (reset == 1'b1)
q <= 1'b0;
else
q <= d;
end
endmodule

//#end -- edit above this line, do not edit this line
##### Connect the Verilog-based Component into the Project

Now, add the component into the project and test it.

1. In the Workspace Explorer panel, click the Source tab, and then double-click the TopDesign.cysch to open the top design schematic file in the Workspace.
2. Placing the Counter:
In the Component Catalog panel, you can see that there has one new EE446 catalog, click on it to change the catalog to EE446. Drag and drop the Shift Right 4-bit component in Digital sub-folder into the TopDesign file as shown in Figure 9.

Figure 9:
Drag and Drop the New Component into the Schematic File
3. Connect other Components with the Counter:
Change the catalog to the Cypress in the Component Catalog panel, and then drag and drop the following components into the schematic files as shown in Figure 10:
• A Digital Input Pin component (Ports and Pins➤Digital Input Pin) with a NOT gate (Digital➤Logic➤Not) to the d terminal
• A Clock source (System➤Clock) to the clk terminal
• A Logic Low '0' component (Digital➤Logic➤Logic Low '0') to the reset terminal
• A Digital Output Pin component (Ports and Pins➤Digital Output Pin) to the q[3:0] terminal.

Figure 10: The TopDesign File
4. Configure Components:
• Double-click on the Digital Input Pin component in the schematic to open the Configure dialog. Edit the name to PIN_IN, and change the Drive Mode to the Resistive Pull Up mode.
• Double-click on the Clock component, configure the clock frequency to 1Hz, and unchecked the Sync with MASTER_CLK in the Advanced tab.
• Double-click on the Digital Output Pin component. Edit the name to PIN_Q, and change the Number of Pins to 4 as shown in Figure. In the Mapping tab, check Display As Bus and then click the OK button.
5. Pin Assignment:
Next step is configuring the pins. From the Workspace Explorer panel, double-click the "Verilog01_ShiftRight.cydwr" to open Design-Wide Resources (DWR). In the Pins tab, assign the pin to the I/Os.
• Assign P3[3:0] to the \PIN_Q[3:0]\
• Assign P2[2] to the PIN_IN.
6. Hardware Connections:
In this step, you need to connect the hardware parts with your PSoC 5LP board. According to the pin assignment at step 5, you need to connect four LEDs with 200Ω (ohm) resistor to the PSoC 5LP board on P3.0 to P3.3 to display the result. The LED have two legs; the longer leg is the positive (anode) pin, and the short leg is the negative (cathode) pin. If your LED legs are trimmed, try finding the flat edge on the LED's outer casing. The pin nearest the flat edge will be the negative, cathode pin. Connect negative pin with a 200Ω resistor and then connect to GND. Connect the positive leg to the port on the board. If you are not using the CY8CKIT-059 kit, you may need a push button, and connects a wire from P2.2 to one leg of the push button, and then connect other leg to the GND.

7. Build the Design:
After completing the design, use the Build button or click the Build➤Build Verilog01_ShiftRight from the menu to generate source code for component's API and compile the project. In this lab, you don't need to add or modify any software source code. If there are errors in your design, PSoC Creator will show all error in the Notice List panel. Click Go To Error tab to find and resolve the errors.
8. Program the Device:
Connect your PSoC 5LP development kit to your computer, and click Program button or click Debug➤Program from the menu to program your design to the PSoC 5LP board.
9. Now, you can press and/or release the switch button on the your PSoC 5LP development kit, and the LED will be turn on/off from P3.3 shifting to P3.0 by every second.

#### Second Verilog Design: 4-bit Shift Right Counter (Using Behavior Modeling)

Now, you need to design an new version of 4-bit Shift Right counter by using behavior modeling only. Follow from the step 2 in the 4-bit Shift Right Component Creating Steps section to create new counter, but you need to change the component name to ShiftRight2_v1_00 at step 3 and enter EE446/Digital/Shift Right 4-bit_v2 in the Catalog Placement dialog at step 7.

In this design, we use behavior modeling to create the ShitRight2 module. The Verilog code as below:

//#start header -- edit after this line, do not edit this line
// ========================================
//
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
include "cypress.v"
//#end -- edit above this line, do not edit this line
// Generated on 01/26/2016 at 10:38
// Component: ShiftRight_V2_00
module ShiftRight_V2_00 (
output reg [3:0] q,
input   clk,
input   d,
input   reset
);

//#start body -- edit after this line, do not edit this line

always @(negedge clk or posedge reset) begin
if (reset == 1'b1)
q = 4'b0;
else
q = {d, q[3:1]};

end
//#end -- edit above this line, do not edit this line
endmodule
//#start footer -- edit after this line, do not edit this line
//#end -- edit above this line, do not edit this line

Next step, delete the old component form the TopDesign schematic file, and drag and drop the new Verilog-based component (Shift Right 4-bit_v2) from the Component Catalog panel to the schematic file. Make sure all the components in the schematic are connected correctly. Then click Build and Program button to test the new Verilog-based component. The result should be same as the first design.