KB 03: Setting CPU Frequency of PSoC 5LP in PSoC Creator

There is one 24MHz XTAL oscillator and one 32.768KHz cystal on the EagleSoC or EagleSoC mini board. These two external clock sources can provide the system with a stable frequency input.

Before you change the CPU frequency, please check the datasheet, make sure what is the max frequency of your PSoC 5LP microcontroller.

There are two methods to set up CPU frequency of PSoC 5LP to 67MHz/80MHz in PSoC Creator: PLL and External Osc.

1. PLL + Internal Low Frequency Sources

In the first method we can use PLL to generate 67MHz frequency to CPU from internal low frequency sources like IMO or Digital Signal. Use the following procedure to set the CPU speed of PSoC 5LP to maximum (67MHz) (or any other desired frequency).

  1. Open the .cydwr file in the project.
  2. In the Clocks tab, click on the Edit Clock button.
  3. In the PLL box, select IMO as the clock source and set desired frequency to 67MHz.
  4. In the Master Clock box, select PLL_OUT as the source and set a divider of 1.
  5. Similarly, set the divider to 1 in the Bus Clock box.

Screen shot below shows the clock configuration.

PSoC5LP 67MHZ PLL

The accuracy of 67MHz PLL output will depend on the accuracy of these low frequency sources. If the low frequency sources have an accuracy of +/- 0.1%, then the PLL output will also have the same accuracy. +/- 0.1% of 67MHz will correspond to 66.933 to 67.067MHz which may slightly exceed the allowable CPU frequency. This is the reason why we are getting the following error message when trying to set PLL Output to 67MHz.

Error:
PLL_OUT is configured to be 67,000MHz +/- 1.000%, (66.330MHz~67.670MHz), which is faster than the max CPU speed of '67.000' MHz for the currently selected device.

Therefore, the maximum allowed PLL Output frequency in PSoC 5LP is 66MHz. For 80MHz version of PSoC 5LP, the max frequence is 79MHz.

 


2. External Frequency Sources

Alternatively, we can use external XTAL clock source to generate the 67MHz or 80MHz to the CPU.

  1. Open the .cydwr file in the project.
  2. In the Clocks tab, click on the Edit Clock button.
  3. Enable XTAL box and configure the clock frequenxy to 24.000 MHz.
  4. In the IMO box, select XTAL as the clock source.
  5. In the PLL box, you can select IMO or XTAL as the clock source and set desired frequency to 67MHz or 80MHz.
  6. In the Master Clock box, select PLL_OUT as the source and set a divider of 1.
  7. Similarly set the divider to 1 in the Bus Clock box.

 PSoC5LP 67MHZ EXT FREQ