FPGA Lab 04: Design of 4-bit ALU and Its Implementation in FPGA

1-bit ALU

1-bit ALU

A large part of ALU design is captured by the design of a 1-bit ALU. Then 1-bit ALUs can be combined to form a multibit ALU with a small amount of additional circuitry. Figure 1 shows the diagram of the basic idea for a 1-bit ALU: produce the different results in parallel, then select one according to the opcode with a multiplexer.

Figure 1: The 1-bit ALU Block Diagram

Each of the OP boxes computes 1-bit for an operation based on the requirement. The multiplexer selects the output of the appropriate 1-bit operation. Its control input aluop is derived from operation and function bits of a machine instruction.

• 1-bit Full Adder
• Adder
• Subtractor
• Bit-wise AND and XOR
• 4-to-1 Multiplexer (MUX)

• 1-bit Full Adder
• Adder
• Subtractor
• Bit-wise AND and XOR
• 4-to-1 Multiplexer (MUX)

1-bit Full Adder

1-bit Full Adder

When two bits a and b are added, a sum and a carry are generated. A combinational circuit that adds two bits only is called a "half adder". However, after adding the least significant bits (bit 0) of the two numbers, the carrying value from the adder needs to be added into the next bit of numbers. On the other hand, addition of three bits (two bits of the two numbers and a previous carry, which may be 0 or 1) is required for all the subsequent bits. A combinational circuit that adds three bits, generating a sum and a carry (which may be 0 or 1), is called a "full adder."

Figure 2 shows the block diagram of a full adder. The full adder adds three bits (a, b, and cin) and generates a sum bit and a carry bit (s and cout).

Table 1: Truth Table of the Full Adder

cin	a	b	cout	s
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

Figure 2: The Logic Circuit of 1-bit Full Adder and the Module Diagram

Adder

Adder

The 1-bit full adder only does single-digit addition. Multiple copies can be used to make adders for any size of binary numbers. By default, the carry-in to the lowest bit adder (LSb, bit 0) is 0. Carry-out of one digit's adder becomes the carry-in to the next highest digit's adder. The carry-out of the most significant bit adder is the carry-out of the entire operation. The 4-bit adder is shown in the following figure.

Figure 3: A 4-bit Binary Adder

Subtractor

Subtractor

We already design full-adder in the circuit, we can use full adder to implement binary subtraction simply by using two's complement on the subtrahend b inputs. In two's complement, a negative can be achieved by inverting a number and adding one ($ - B = \overline B + 1$.) To subtract a number B from A, invert B and add 1 to it, then proceed to add that sum to A.

$$A - B = A + \overline B + 1$$

In order to transform a normal adder into a subtractor, we need to invert the second operand (B) and add 1 (by setting $cin = 1$ at least significant bit, bit 0). A 4-bit adder-subtractor can be achieved by using the following circuitry.

Figure 4: A 4-bit Adder-Subtractor

When the control signal $sub = 0$, the circuit is an adder.

A = A
B = B
Cin = 0

Therefore, the computed sum will be A + B + Cin = A + B.

When $sub = 1$, the circuit becomes a subtractor.

A = A
B = ~B
Cin = 1

Meaning the computed sum will be A + ~B + Cin = A + ~B + 1 = A - B, hence achieving subtraction.

Bit-wise AND and XOR

Bitwise AND and XOR

To perform bitwise-and and -xor operation, add one logical AND and one XOR gate to the circuitry.

Figure 5: A 1-bit Bitwise-AND and -XOR Circuitry

4-to-1 Multiplexer (MUX)

4-to-1 MUX (Multiplexer)

A MUX (multiplexer) is a combinational logic circuit for selecting among several possible input signals as shown in Figure 6.

Figure 6: A 4-to-1 MUX

This 4-to-1 MUX has four signal inputs: in0, in1, in2, and in3. A MUX can in principle have any number of signal inputs. The control or select input sel determines which of the signal inputs appears as the output Out. It has as many bits as needed for the selection. One bit selection suffices for just 2 signal inputs, 2 bits selection suffices for 3 or 4 signal inputs, and 3 bits selection suffices for 5 to 8 signal inputs.

The MUX output out can be a multi-bit signal. Each of the signal inputs has the same number of bits as the output.

Now, let us look at Table 1 and determine for which values of aluop we perform an operation from which type. It should be clear that when aluop[1] is logic 0, we have an arithmetic operation and when aluop[1] is logic 1, we select a logic operation. In the arithmetic part, we realize that we have an addition or a subtraction. We can see that aluop[0] is logic 0 for additions and logic 1 for subtraction. Therefore, the aluop[0] can be used for the control signal sub as shown in Figure 4 (in the "Subtractor" tab).

According to the above information about the ALU, we can draw a module diagram that will implement the 1-bit ALU operations listed in Table 1.

Figure 7: The Top-Level Module of 1-bit ALU Module

Once we have a good module diagram it is straightforward to implement the circuit in Verilog. Replace each block in the diagram with a Verilog description and use the signal names in the module diagram.

1. Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
   • Working directory: <the folder you created for this lab>/Lab04_01_1bit_ALU
   • The name of the project: ALU_1bit
   • The name of the top-level design: ALU_1bit
2. Add a new Verilog HDL file, type and finish the Verilog code shown in the following code. You may need to add some wire, regs, or any other logic gates as needed.
   
   • Implement the fullAdder_1bit module by using gate-level modeling (see Figure 2, in the "1-bit Full Adder" tab)
   • Implement the mux_4to1_1bit module by using dataflow modeling (see Figure 6, in the "4-to-1 Multiplexer (MUX)" tab)
   • Connect all modules in the ALU_1bit module as Figure 7.

   module ALU_1bit(a, b, cin, aluop, cout, aluout);
   input a, b, cin;
   input [1:0] aluop;
   output cout, aluout;
   
   wire sum, aANDb, aXORb;
   
   fullAdder_1bit FA(.a(), .b(), .cin(), .cout(), .s());
   and U1();
   xor U2();
   xor U3();
   mux_4to1_1bit U4(.in0(), .in1(), .in2(), .in3(), .sel(), .out());
   
   endmodule
   //----------------------------------------------------
   module fullAdder_1bit(a, b, cin, cout, s);
   input a, b, cin;
   output cout, s;
   
   // Using Gate-Level Modeling to implement 1-bit full adder
   
   endmodule
   //----------------------------------------------------
   module mux_4to1_1bit(in0, in1, in2, in3, sel, out);
   input  in0, in1, in2, in3;
   input [1:0] sel;
   output out;
   
   // Using Dataflow modeling to implement 4-to-1 MUX
   assign out = ;
   
   endmodule
   

3. Save all files, then compile the code. If there are no errors, using RTL Viewer to check the synthesized circuit correct or not. It should be the same as our top-level diagram. Capture and save all RTL diagrams to disk.

4-bit ALU

To build a 4-bit ALU module, we need to combine four 1-bit ALU modules and implement a circuit for overflow signal. The module diagram is shown in Figure 8.

Figure 8: The Top-Level Module of 4-bit ALU

1. Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
   • Working directory: <the folder you created for this lab>/Lab04_02_4bit_ALU
   • The name of the project: ALU_4bit
   • The name of the top-level design: ALU_4bit
   • In the Add Files window, add ALU_1bit.v file to the project.
2. Add a new Verilog HDL file, type and finish the Verilog code shown in the following code.
   
   • Connect all modules in the ALU_4bit module as Figure 8. You may need to add some wire, regs, or any other logic gates as needed.

   module ALU_4bit(a, b, aluop, z, overFlow, carryOut);
   input  [3:0] a;
   input  [3:0] b;
   input  [1:0] aluop;
   output [3:0] z;
   output overFlow, carryOut;
   
   wire cout0, cout1, cout2, cout3;
   
   ALU_1bit bit0 (.a(), .b(), .cin(), .aluop(), .cout(), .aluout());
   ALU_1bit bit1 (.a(), .b(), .cin(), .aluop(), .cout(), .aluout());
   ALU_1bit bit2 (.a(), .b(), .cin(), .aluop(), .cout(), .aluout());
   ALU_1bit bit3 (.a(), .b(), .cin(), .aluop(), .cout(), .aluout());
   
   xor U5 ();
   
   endmodule

3. Save all files, then compile the code. If there are no errors, using RTL Viewer to check the synthesized circuit correct or not. It should be the same as our top-level diagram. Capture and save all RTL diagrams to disk.

Two's Complement Decoder

We want to display the input values and result on the 7-segment displays. But the values in the system are signed integers, which means the most significant bit (MSb) is used for the sign bit. When the sign bit is zero, the value is a positive number. When sign bit is one, the value is a negative number, which means it is a two's complement number. We need to convert the two's complement value to the normal binary value with a negative signal. The module diagram is shown in Figure 9.

Figure 9: The Module Diagram of Two's Complement Decoder

The functionality of the two's complement decoder as below:

• The sign bit is in the Most Significant bit (MSb).
• If the input value is a positive number (which means the sign bit is zero), then pass the input number to output and set the sign signal to zero.
• If the input value is a negative number (which means the sign bit is one), then the input value must convert to normal binary value by inverting the number and adding one and set the sign signal to one.

1. Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
   • Working directory: <the folder you created for this lab>/Lab04_03_TwoComplement
   • The name of the project: twoComp
   • The name of the top-level design: twoComp
2. Add a new Verilog HDL file, type and finish the Verilog code shown in the following code.
   Using dataflow modeling to implement the twoComp module. You may need to add some wire, regs, or any other logic gates as needed.
   

   module twoComp(bin, bout, sign);
   input  [3:0] bin;
   output [3:0] bout;
   output sign;
   
   assign sign = _____ ;
   assign bout = _____ ? _____ : _____ ;
   
   endmodule

Integrate all submodules to the Top-Level Module

Top-Level Module

The module of a sequential machine, Caculator_4bit_top, is depicted in Figure 1, with the input and output ports that interface the module to its environment.

Figure 1: Top-Level Module Diagram for 4-bit Calculator Design

1. Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
   • Working directory: <the folder you created for this lab>/Lab04_4bitCalculator
   • The name of the project: calculator_4bit
   • The name of the top-level design: calculator_4bit_top
   • In the Add Files window, add hex7seg.v, ALU_1bit.v, ALU_4bit.v and twoComp.v files to the project.
2. Add a new Verilog HDL file, type and finish the Verilog code shown in the following code.
   Connect all submodules and necessary components into the top-level module. You may need to add some wire, regs, or any other logic gates as needed.
   

   module calculator_4bit_top(SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);
   input  [9:0] SW;
   output [9:0] LEDR;
   output [7:0] HEX0;
   output [7:0] HEX1;
   output [7:0] HEX2;
   output [7:0] HEX3;
   output [7:0] HEX4;
   output [7:0] HEX5;
   
   wire [3:0] a; wire [3:0] aout;
   wire [3:0] b; wire [3:0] bout;
   wire [3:0] z; wire [3:0] zout;
   wire carryOut, overFlow, signa, signb, signz;
   
   // Turn off 7-Segment Dispaly [dp, a,b,c,d,e,f] for HEX1, HEX3, and HEX5
   
   
   ALU_4bit U10 (.a(), .b(), .aluop(), .z(), .overFlow(), .carryOut());
   
   twoComp  U11 (.bin(), .bout(), .sign());
   twoComp  U12 (.bin(), .bout(), .sign());
   twoComp  U13 (.bin(), .bout(), .sign());
   
   hex7seg  U14 (.hex(), .a(), .b(), .c(), .d(), .e(), .f(), .g(), .dp());
   hex7seg  U15 (.hex(), .a(), .b(), .c(), .d(), .e(), .f(), .g(), .dp());
   hex7seg  U16 (.hex(), .a(), .b(), .c(), .d(), .e(), .f(), .g(), .dp());
   
   endmodule
   

3. Save all files, then compile the code. If there are no errors, using RTL Viewer to check the synthesized circuit correct or not. It should be the same as our top-level diagram. Capture and save all RTL diagrams to disk.