**FPGA Lab 01:** 1-bit ALU Design Using Gate-Level (Structural) Model

### Objective:

- Design and build 1-bit ALU with addition (ADD), subtraction (SUB), logical AND, OR operations
- Using logic hierarchy to develop your design

- Using logical gate modeling to design all components

- Learn to use the Verilog HDL to design the ALU

### Introduction

The ALU performs arithmetic and logic operations. It is a fundamental building block of the CPU of a computer, and it is a combinational logic circuit.

In this lab, you need to design an 1-bit ALU by using gate-level (structural) modeling. Inside of ALU, we need one full-adder, one MUX, and other logical gates to perform the logic operations.

### Preparation

## 1. Implement AND and OR operations

First, add AND and OR logical operations into your 1-bit ALU. The truth tables for **AND** and **OR** gates as shown in Figure 1.

**Figure 1**: The Truth Table for Logic AND and OR Gates

The design principles are:

- A number of functions are performed internally, but only one result is chosen for the output of ALU.
- In this circuit, you just need one
**AND** gate, one **OR** gate and one **MUX**.
- The MUX is used for selection which operations will be execuated by ALU.

Please draw your design in the Diagram 1.

Diagram 1: The Schematic Circuit for AND and OR Operations

## 2. Design the Full Adder Circuit

##### Full Adder Circuit Design

The Full Adder has three inputs and two outputs as shown in Figure 2.

**Inputs**:

Two inputs for number **a** and number **b** and a **c**_{in} (Carry-In) input
**Outputs**:

The outputs are the **sum** and **c**_{out} (Carry-out). The **sum** is the addition of **a**, **b** and **c**_{in}.

Figure 2: The Full Adder Component Block

Please fill the truth table for Full Adder in Table 1. Then uses K-Maps to simplify the logical equations for output **sum** and **c**_{out} pins. Write down your final equations in SOP or POS format.

**Table 1:** Full Adder Truth Table

**Table 2:** K-Maps for Output **sum** and **c**_{out}

##### The Circuit of Full Adder

From the truth table and after minimization, you can design the **sum** and **c**_{out} by using logical gates: **AND**, **OR**, **XOR** and **NOT** gates. Please draw your design in diagram 1, and also define all wires with a unique net-name.

Diagram 2: The Schematic Circuit for 1-bit Full Adder

## 3. Implement Subtraction function

In the computer field, we use two's complement numeric system to represent the negative number. The two's complement theory says to invert each bit with a **NOT** gate, then add one. For the *n*-bit **A** and **B**, **(A - B)** can be implemented by converting subtrahend **B** to an negative number (2's complement format), the uses adder to add **A** with **(-B)**. The idea is shown as following equation:

The idea are:

- Invert bit
**b** when ALU perform subtraction
- Therefore, a switch will be added to select either original
**b** value or **Inverted b** value to the input of the Adder. The control pin for the switch (**MUX**) is named as "**b**_{inv}"
- When the subtraction is performed, the
**c**_{in} of the Least Significant Bit (Low-Order Bit) must be 1

Please draw your design in Diagram 3.

Diagram 3: The Schematic Circuit for Subtraction

## 4. Combine 4-to-1 channel Multiplexer design

Now, combine the diagram 1, and 3 together. The MUX component in the diagram 1 needs to exten to 4-to-1 MUX.

Please draw your design in diagram 4.

## 5. 4-to-1 channel Multiplexer design

A **Multiplexer** (or **MUX**) is a device that selects one of serval input signals and forwards the selected input into a output single line. A MUX of *2*^{n} inputs has *n* select lines, which are used to select which input line to send to the output. An electronic MUX can be considered as a multiple-input, single-output switch. It is also called a **data selector**, and can be used to implement Boolean functions of multiple variables.

A 4-to-1 MUX has a boolean equation where **a**_{0} , **a**_{1}, **a**_{2}, and **a**_{3} are the four inputs, **sel** is the selector inputs, and **z** is the output. Which can be expressed as a truth table as shown in Figure 4.

**Figure 4**: 4-to-1 MUX

These tables show that when **sel** = 2'b**00** ➤ z = **a**_{0}, **sel** = 2'b**01** ➤ z = **a**_{1}, **sel** = 2'b**10** ➤ z = **a**_{2}, and **sel** = 2'b**11** ➤ z = **a**_{3},.

## 5. Combine all diagrams design to implement 1-bit ALU

Design the 1-bit ALU using the Full Adder, a MUX and logic gates.

**Diagram 5**: The 1-bit ALU Circuit with Control Bits (ALUOpcode)

Table 3 is the ALU Operation Code.

**op**_{1} |
**op**_{0} |
**Function** |

0 |
0 |
**AND** |

0 |
1 |
**OR** |

1 |
0 |
**ADD** |

1 |
1 |
**SUB** |

**Table 3**: The ALU Operation Code

### Procedure

##### 1. Design the 1-bit Full Adder in Verilog code using Gate Level Modeling

Based on the Diagram 2, specify your design as a Verilog Module using build-in logic primitives (and, not, or) as building blocks. Please study the Verilog Tutorial and the Verilog Presentation Slides for details.

module fulladder1b(a, b, cin, cout, sum);
// Port Declarations
input a, b, cin;
output cout, sum;
// Internal signal declaractions
// Logic declaractions using built-in primitives
endmodule

**Code 1**: 1-bit Full Adder Verilog Code

##### 2. Design 4-to-1 Mux Module using Dataflow Modeling

Using Dataflow modling to design the 4-to-1 MUX.

module mux_41(in0, in1, in2, in3, in4, sel, out);
// Port Declarations
input in0, in1, in2, in3, in4;
input [1:0] sel;
output out;
endmodule

**Code 2**: 4-to-1 MUX

3. Implement 1-bit ALU Module

### Report

### Summary