FPGA Lab 01: 1-bitDesign Using Gate-Level (Structural) Model
- Design and build 1-bit ALU with addition (ADD), subtraction (SUB), logical AND, OR operations
- Using logic hierarchy to develop your design
- Using logical gate modeling to design all components
- Learn to use the Verilog HDL to design the ALU
The ALU performs arithmetic and logic operations. It is a fundamental building block of theof a computer, and it is a combinational logic circuit.
In this lab, you need to design an 1-bit ALU by using gate-level (structural) modeling. Inside of ALU, we need one full-adder, one MUX, and other logical gates to perform the logic operations.
1. Design the 1-bit Full Adder in Verilog code using Gate Level Modeling
Based on the Diagram 2, specify your design as a Verilog Module using build-in logic primitives (and, not, or) as building blocks. Please study the Verilog Tutorial and the Verilog Presentation Slides for details.
module fulladder1b(a, b, cin, cout, sum); // Port Declarations input a, b, cin; output cout, sum; // Internal signal declaractions // Logic declaractions using built-in primitives endmodule
Code 1: 1-bit Full Adder Verilog Code
2. Design 4-to-1 Mux Module using Dataflow Modeling
Using Dataflow modling to design the 4-to-1 MUX.
module mux_41(in0, in1, in2, in3, in4, sel, out); // Port Declarations input in0, in1, in2, in3, in4; input [1:0] sel; output out; endmodule
Code 2: 4-to-1 MUX
3. Implement 1-bit ALU Module