# FPGA Lab 01: Decoder Design Using Verilog Gate-Level Modeling

Gate-level (structural) modeling can be used to write Verilog code for small designs. Especially you already have the logical circuit. In this lab, you will design a 2-to-4 decoder using gate-level modeling, and verify the design on the FPGA board. Then, you will build a 4-to-16 decoder using four 2-to-1 decoders.

## Objectives

• Learn Verilog gate-level modeling
• Understand the structure of the modules

## Background Information

A decoder is a combinational circuit, and it takes an n-bit binary number and produces a minterm or maxterm output on one of ${2^n}$ output lines. Decoders are typically used for computer memory address decoding, which is used to selects different banks of memory and I/O devices. The common TTL/CMOS decoders are as follows:

• 74138: a 3-to-8 line decoder with three enable pins.
• 74139: a dual 2-to-4 line decoder with active low enable pins.
• 74154: a 4-to-16 line decoder with two active-low enable pins.

#### Designing of 2-to-4 Line Decoder Circuit

Let us design a 2-to-4 line decoder that generates maxterm output with an active-low enable pin, as shown in Figure 1. This decoder generates a maxterm when enable by LOW. Table 1 provides the truth table. In the truth table, the symbol X is the don't care condition, which can be 0 or 1. Also, $\overline {EN} = 1$ disables the decoder. On the other hand, the decoder is enabled when $\overline {EN} = 0$. For example, when $\overline {EN} = 0, X0 = 0, X1 = 1$, then the output $\overline {Y2}$ is 0 while the other output $\overline {Y0}$, $\overline {Y1}$, and $\overline {Y3}$ are 1's, and we can say that the decoder has generated the maxterm ${m_3}$.

Figure 1: 2-to-4 Decoder Generating Maxterms
Table 1: Truth Table of the 2-to-4 Decoder Generating Maxterms

Figure 2: Logic Diagram of the 2-to-4 Decoder

#### Designing a 4-to-16 Decoder Using 2-to-4 Decoders

Usually, we will break more complicated circuits into small and simpler components, and then combine the small components to implement the original complex circuits. Hence, large decoders can be designed using small decoders as the building blocks. For example, a 4-to-16 decoder can be designed using five 2-to-1 decoders as shown in Figure 3, and the truth table for the 4-to-16 decoder is provided in Table 2.

Figure 3: Implementation of a 4-to16 Decoder Using 2-to-4 Decoders
Table 2: Truth Table of the 4-to-16 Decoder Generating Maxterms