FPGA Lab 02: 2-bit Comparators Using Different Verilog Modelings

Objectives

Verilog is the Hardware Description Language (HDL) that is used to model the digital systems. In this lab, you will use the following four modelings to design the digital system.

  • Design with gate-level modeling
  • Dataflow modeling design
  • Design with behavioral modeling
  • Mixed design

Required Reading Material

Components Required

  • DE10-Lite Board

Background Information

Verilog has three primary modeling ways: Gate-level, Dataflow, and Behavioral modeling. You can use one of the modelings to design the digital system or mix two or more modelings in the design. In this lab, you have to implement a two-bit comparator with different modeling styles, which generate the output '1' if the numbers are equal. Otherwise, the output set to '0'.

1-bit Comparator

A 1-bit comparator, also called a single bit comparator, consists of two inputs (each for two single-bit numbers) and one output to generate an equal or unequal result between the two binary numbers. The truth table and logic circuit for a 1-bit comparator are given below:

circuit 1bitcomparator
Figure 1: The Truth Table and Logic Circuit for a One-bit Comparator

2-bit Comparator

A 2-bit comparator used to compare two binary numbers each of two bits. It consists of four inputs and one output to generate an equal or unequal result between the two binary numbers. You may think that the quick design way is to use two 1-bit comparators to build a 2-bit comparator: one to compare bit-0 on the two numbers, another to compare the bit-1 on the two numbers. If both number's bit-0 and both number's bit-1 are the same, then the two 1-bit comparator outputs will be '1', which means that the two numbers are completely equal. Connect both outputs of the 1-bit comparator to a AND gate to get the final result.

To prove your thought, let us create a truth table for 4-bit input and one-bit output of the 2-bit comparator. After simplifying the output boolean expression by using the K-map, the result shows that the 2-bit comparator can be built by two 1-bit comparators and an AND gate. The logic circuit of the 2-bit comparator is shown in Figure 2.

circuit 2bitcomparator
Figure 2: The Logic Circuit of the 2-bit Comparator

You have to program the code to the FPGA board and using onboard switches and LEDs to verify the design. In the top design, there are four input signals and one output signal. we can assign the SW[1:0] to the first 2-bit input number b[1:0], SW[3:2] to the second 2-bit input a[1:0], and the output eq signal to the LEDR[0] pin.

Lab Experiments

Let us design a 2-bit comparator with different Verilog modelings.

  1. The top-module diagram as below:

topModuleDiagram
Figure 3: The Top-Module Diagram

Based on the module diagram to design the top-module code.

  1. Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
    • Working directory:  <the folder you created for this lab>/Lab02_comparator
    • The name of this project: cmp_2bit
    • The name of the top-level design: cmp_2bit_top
  2. Add a new Verilog HDL files for top-module to the project.
    • The top-level module is used to connect the 2-bit comparator to the external switches and LED. Enter the Verilog codes as below, and save the file as cmp_2bit_top.v.
      // This is the top-module
      module cmp_2bit_top (SW, LEDR);
      input  [9:0] SW;
      output [9:0] LEDR;
      
      // Your Verilog here: Connect 2bit comparator modules
      // cmp_2bit_g cmp1(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[0]));
      // cmp_2bit_d cmp2(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[1]));
      // cmp_2bit_b cmp3(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[2]));
      // cmp_2bit_m cmp4(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[3]));
      
      endmodule
  3. Import assignment file (DE10_Lite.qsf). Before clicking the OK button, make sure the item Global assignments in the Advance Import Settings must be checked.
  4. Save the project, then follow the instructions to build a 2-bit comparator using different Verilog modeling styles.