FPGA Lab 02: 2-bit Comparators Using Different Verilog Modelings
Objectives
Verilog is the Hardware Description Language (HDL) that is used to model the digital systems. In this lab, you will use the following four modelings to design the digital system.
- Design with gate-level modeling
- Dataflow modeling design
- Design with behavioral modeling
- Mixed design
Required Reading Material
Components Required
Background Information
Verilog has three primary modeling ways: Gate-level, Dataflow, and Behavioral modeling. You can use one of the modelings to design the digital system or mix two or more modelings in the design. In this lab, you have to implement a two-bit comparator with different modeling styles, which generate the output '1' if the numbers are equal. Otherwise, the output set to '0'.
1-bit Comparator
A 1-bit comparator, also called a single bit comparator, consists of two inputs (each for two single-bit numbers) and one output to generate an equal or unequal result between the two binary numbers. The truth table and logic circuit for a 1-bit comparator are given below:
Figure 1: The Truth Table and Logic Circuit for a One-bit Comparator
2-bit Comparator
A 2-bit comparator used to compare two binary numbers each of two bits. It consists of four inputs and one output to generate an equal or unequal result between the two binary numbers. You may think that the quick design way is to use two 1-bit comparators to build a 2-bit comparator: one to compare bit-0 on the two numbers, another to compare the bit-1 on the two numbers. If both number's bit-0 and both number's bit-1 are the same, then the two 1-bit comparator outputs will be '1', which means that the two numbers are completely equal. Connect both outputs of the 1-bit comparator to a AND gate to get the final result.
To prove your thought, let us create a truth table for 4-bit input and one-bit output of the 2-bit comparator. After simplifying the output boolean expression by using the K-map, the result shows that the 2-bit comparator can be built by two 1-bit comparators and an AND gate. The logic circuit of the 2-bit comparator is shown in Figure 2.
Figure 2: The Logic Circuit of the 2-bit Comparator
You have to program the code to the FPGA board and using onboard switches and LEDs to verify the design. In the top design, there are four input signals and one output signal. we can assign the SW[1:0] to the first 2-bit input number b[1:0], SW[3:2] to the second 2-bit input a[1:0], and the output eq signal to the LEDR[0] pin.
Lab Experiments
Let us design a 2-bit comparator with different Verilog modelings.
- The top-module diagram as below:
Figure 3: The Top-Module Diagram
Based on the module diagram to design the top-module code.
- Launch the Quartus Prime software and create a new project. The following lists are the settings for the project.
- Working directory: <the folder you created for this lab>/Lab02_comparator
- The name of this project: cmp_2bit
- The name of the top-level design: cmp_2bit_top
- Add a new Verilog HDL files for top-module to the project.
- The top-level module is used to connect the 2-bit comparator to the external switches and LED. Enter the Verilog codes as below, and save the file as cmp_2bit_top.v.
// This is the top-module
module cmp_2bit_top (SW, LEDR);
input [9:0] SW;
output [9:0] LEDR;
// Your Verilog here: Connect 2bit comparator modules
// cmp_2bit_g cmp1(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[0]));
// cmp_2bit_d cmp2(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[1]));
// cmp_2bit_b cmp3(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[2]));
// cmp_2bit_m cmp4(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[3]));
endmodule
- Import assignment file (DE10_Lite.qsf). Before clicking the OK button, make sure the item Global assignments in the Advance Import Settings must be checked.
- Save the project, then follow the instructions to build a 2-bit comparator using different Verilog modeling styles.
Exp#1: Gate-Level Modeling
The first experiment is to design a 2-bit comparator, which contains two 1-bit comparators. The design architecture as follows:
Figure 4: The Design Architecture for Experiment #1
Here, we use the bottom-up design: the first design is the 1-bit comparator at the bottom level, the next design is the 2-bit comparator at the middle level, then connect a 2-bit comparator module in the top-level module.
- The module diagrams as below:
Figure 3: The 2-bit comparator Module Diagram and Sub-Module Diagram using Gate-Level Modeling
- Implement a 1-bit comparator first.
Add a new Verilog HDL Files to the project. Enter the Verilog codes as below, and save the file as cmp_1bit.v.
// filename: cmp_1bit.v
// description: Implement the 1-bit comparator using gate-level modeling
// modeling: Gate-level modeling
// algorithm: if both bits are equal, eq = 1, otherwise eq = 0.
// author: Your name
module cmp_1bit(a, b, eq);
input a, b;
output eq;
// Your Verilog Here
endmodule
- Once finished the 1-bit comparator, then continue to implement the 2-bit comparator. The 2-bit comparator consists of two 1-bit comparators.
Add a new Verilog HDL Files to the project. Enter the Verilog codes as below, and save the file as cmp_2bit_g.v.
// filename: cmp_2bit_g.v
// description: Implement the 2-bit comparator by using two cmp_1bit.v components
// modeling: Gate-level modeling
// algorithm: if both results from cmp_1bit are 1, eq = 1, otherwise eq = 0.
// author: Your name
module cmp_2bit_g (a, b, eq);
input [1:0] a;
input [1:0] b;
output eq;
// Your Verilog here
endmodule
- Modify the top module code to connect the cmp_2bit_g module.
- In the Quartus menu, select Processing ➤ Start Compilation, or click
button to compile the code. If no syntax error, a successful window will appear as below:
Then click OK to close the window.
- The FPGA IDE will synthesize circuits specified using high-level languages, like Verilog HDL, to a Register Transfer Level (RTL) specification, which can be used as input to a gate-level logic synthesis flow. Quartus Prime software provides the RTL Viewer that can display a block diagram view of a circuit, at the level of registers, flip-flops and functional blocks that constitute the design. Let us check the final synthesized circuits at the RTL level; select Tools ➤ Netlist Viewers ➤ RTL Viewer to create the RTL circuit. Then, you will see an RTL circuit that should look similar to the top module diagram we designed. Double-click on each block to open the module and check the RTL circuit correct or not. Capture and save all RTL diagrams to disk. If any wires are missing in the RTL window, go back to check the Verilog code.
- Finally, program the code to the FPGA board, change the SW[3:0] state to check the results. Show the results to your instructor.
Exp#2: Dataflow Modeling
Dataflow modeling provides the means of describing combinational circuits by their boolean expression rather than by their gate structure.
In Figure 2, after simplify the equation, the boolean express for eq is: $eq = ({a_1} \otimes {b_1})({a_0} \otimes {b_1})$. We know that the XNOR function is the inverse of the XOR functiob. The eq expression can be rewritten as $eq = (\overline {{a_1} \oplus {b_1}} )(\overline {{a_0} \oplus {b_1}} )$.
The model design diagram is shown in the following Figure:
Figure 4: The Module Diagram for 2-bit Comparator Module using Dataflow Modeling
- Add a new Verilog HDL File, enter the following code in the editor panel, then save the file as cmp_2bit_d.v.
module cmp_2bit_d(a, b, eq);
input [1:0] a;
input [1:0] b;
output eq;
// Your Verilog code here
endmodule
- In the top module code, comment out the previous connection code, then connect the cmp_2bit_d module.
- Compile the code. If there are no errors. using RTL Viewer to check the synthesized circuit correct or not. Capture and save all RTL diagrams to disk.
- Program the code to the FPGA board, test and show the results to the instructor.
Exp#3: Behavioral Modeling
Usually, the behavioral modeling is used for the sequential logic circuit, but it also can be used for the combinational circuit. The behavioral statements must be inside the always block or initial block, and the output of the assignment statement must be of the reg data type.
The following procedures help you to find the functions of a circuit:
- Find out all relationships between inputs and outputs.
- Any sequence activity on the output.
- Look for high priority and critical signals.
- For synchronous and asynchronous circuit, draw the timing diagram.
Write all you found in human-readable language on the paper. Then, use pseudocode to rewrite the sentences into process steps. Don't forget to handle high priority and critical signals first.
Let us analyze the function of the 2-bit comparator:
- It is a simple combinational circuit and no high priority signal.
- Output value depends on the value of the input. If input values are same, then output to 1, otherwise output to 0;
The pseudocode for the 2-bit comparator as below:
if a is equal to b
eq = 1
else
eq = 0
- Add a new Verilog HDL File, enter the following template code in the editor panel, then save the file as cmp_2bit_b.v. The template code is not completed. Convert the pseudocode to Verilog behavioral statements in the always block to complete the function.
module cmp_2bit_b (a, b, eq);
input [1:0] a;
input [1:0] b;
output eq;
always @(a or b) begin
//
end
endmodule
- Compile the code. If there are no errors. using RTL Viewer to check the synthesized circuit. Capture and save all the RTL Viewer diagrams to disk.
- Program the code to the FPGA board, test and show the results to the instructor.
Exp#4: Mixed Modelings
If needed, you can mix all the modeling styles together into one module. The module diagram as follow:
There are two 1-bit comparators in the module; bit 0 comparator is implemented by using behavioral modeling, another comparator to compare bit 1 is implemented by dataflow modeling. Than use gate-level modeling to connect the results to the eq signal.
- Add a new Verilog HDL file, save the file as cmp_2bit_m.v.
module cmp_2bit_m(a, b, eq);
input [1:0] a;
input [1:0] b;
output eq;
reg eq0;
wire eq1;
// Using behavioral modeling to implement 1-bit comparator for a[0] & b[0]
always @(a[0] or b[0]) begin
end
// Using dataflow modeling to implement 1-bit comparator for a[1] & b[1]
// Using get-level modeling to get the final result to the eq signal
endmodule
- In the top module code, comment out the previous connection code, then connect the cmp_2bit_m module.
- Compile the code. If there are no errors. using RTL Viewer to check the synthesized circuit correct or not. Capture and save all RTL diagrams to disk.
- Program the code to the FPGA board, test and show the results to the instructor.
Exp#5: Connect All Modules and Check the Final Implementation Circuit in FPGA
Now, connect all 2-bit comparators in the top-module code as below. Compile the code and then open the RTL Viewer. Using RTL Viewer is a good way to view your synthesis results to determine whether you have created the necessary logic and that the logic and connections have been interpreted correctly by the software.
// Your Verilog here: Connect 2bit comparator modules
cmp_2bit_g ic1(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[0]));
cmp_2bit_d ic2(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[1]));
cmp_2bit_b ic3(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[2]));
cmp_2bit_m ic4(.a(SW[3:2]), .b(SW[1:0]), .eq(LEDR[3]));
Technology Mapped Netlist Viewer
Quartus Prime also provides another netlist viewer to help the designer to analyze design problems - the Technology Map Viewer. The Technology Map Viewer shows how the digital circuit is implemented inside FPGA.
The logic designs are ultimately implemented in Look-Up Tables and other "atom primitives" on the FPGA. You can view this using the Technology Map Viewer by select Tools ➤ Netlist Viewers ➤ Technology Map Viewer (Post-Fitting). The Technology Map Viewer provides a technology-specific graphical representation of your design after Analysis & Synthesis. It shows the hierarchy of atom primitives (LUTs, I/O ports, memories, etc.) in your design.
In the top-level diagram of the Technology Map Viewer, double-click on the logic element to see the detail element's design. Inside the element, you will see a single logic cell component. Right-click on the single logic cell in the design and select Properties. The Properties window will appear on the left. It will show the logic-gate equivalent of the look-up table, the truth table for the LUT, its equivalent equation, and more.
You should include the following items in the report:
- Capture the top-level diagram of the RTL Viewer and paste it in your report. How many logic elements in the RTL Viewer diagram?
- Capture the top-level diagram of the Technology Map Viewer and paste it in your report. And capture the logic-gate equivalent in the Properties window in the report. Explain why only one logic element in the top-level diagram?
- In the Properties window, select the Truth Table tab on the bottom, copy the table in your report. Check the connection between the logic element and the output ports. Then, explain the values in the truth table.
