FPGA Lab 04: Design of 4-bit ALU and Its Implementation in FPGA


  • Learn how to implement an Arithmetic Logic Unit (ALU) in Verilog.

Background Information

An Arithmetic Logic Unit (ALU) is a combinational circuit that performs logical and arithmetic operations on a pair of n-bit operands. The inputs a and b are signed, two's complement numbers when they are presented to the input of the ALU. The operations performed by an ALU are controlled by a set of operation-select inputs. In this lab, you will design a 4-bit ALU with 2 operation-select inputs, aluop[1:0]. Logical operations take place on the bits that comprise a value (known as bitwise operations), while arithmetic operations treat inputs and outputs as two's complement integers. If an addition results in overflow, enable the Overflow output. The different operations will be selected by a 2-bit control signal called "aluop" according to the following Table.

Table 1: ALU Functions

aluop[1:0] result = Description
00 a + b Addition
01 a - b Subtraction
10 a and b Bit-wise and
11 a xor b Bit-wise xor

Lab Experiment

This lab required the design and construction of a 4-bit ALU with the following specifications using Verilog HDL.

  • ALU has two 4-bit inputs operands.
  • ALU performs operations such as addition, subtraction, AND and XOR on the two input operands depending on control lines.
  • ALU provides an overflow error when the result of any operation exceeds the range of output words.
  • ALU provides a carry-out signal.

Using Bottom-Up Design

In a bottom-up design flow, the entire design is compiled in separate projects and locked down once the designer has achieved timing closure on the blocks. The lower-level partitions are then imported into the top-level project for final integration.

Test and Check The Results

Program the code to the board, and use the following input values in the Table to test your code:




A value
Displayed on
B value
Displayed on
Z value
Displayed on
Z value
in Binary


00 (Add)01011100
00 (Add)11110101
00 (Add)10100011
00 (Add)11011010
01 (Sub)01011100
01 (Sub)11110101
01 (Sub)10100011
01 (Sub)11011010
10 (And)01011100
10 (And)11110101
10 (And)10100011
10 (And)11011010
11 (Xor)01011100
11 (Xor)11110101
11 (Xor)10100011
11 (Xor)11011010

Record the results in the table, and use the calculator to check with your results (correct or not).