**FPGA Lab 04: Design of 4-bit ALU and Its Implementation in FPGA**

**Objectives**

- Learn how to implement an Arithmetic Logic Unit (ALU) in Verilog.

**Background Information**

An Arithmetic Logic Unit (ALU) is a combinational circuit that performs logical and arithmetic operations on a pair of n-bit operands. The inputs ** a** and

**are signed, two's complement numbers when they are presented to the input of the ALU. The operations performed by an ALU are controlled by a set of**

*b**operation-select*inputs. In this lab, you will design a 4-bit ALU with 2 operation-select inputs,

**aluop[1:0]**. Logical operations take place on the bits that comprise a value (known as

*bitwise*operations), while arithmetic operations treat inputs and outputs as two's complement integers. If an addition results in overflow, enable the

**Overflow**output. The different operations will be selected by a 2-bit control signal called "

**aluop**" according to the following Table.

**Table 1**: ALU Functions

aluop[1:0] |
result = |
Description |

00 | a + b | Addition |

01 | a - b | Subtraction |

10 | a and b | Bit-wise and |

11 | a xor b | Bit-wise xor |

**Lab Experiment**

This lab required the design and construction of a 4-bit ALU with the following specifications using Verilog HDL.

- ALU has two 4-bit inputs operands.
- ALU performs operations such as addition, subtraction, AND and XOR on the two input operands depending on control lines.
- ALU provides an overflow error when the result of any operation exceeds the range of output words.
- ALU provides a carry-out signal.

**Using Bottom-Up Design**

In a bottom-up design flow, the entire design is compiled in separate projects and locked down once the designer has achieved timing closure on the blocks. The lower-level partitions are then imported into the top-level project for final integration.

**Test and Check The Results**

Program the code to the board, and use the following input values in the Table to test your code:

ALUOP SW[9:8] | A SW[7:4] | B SW[3:0] | A value Displayed on HEX5, HEX4 | B value Displayed on HEX3, HEX2 | Z value Displayed on HEX1, HEX0 | Z value in Binary LEDR[3:0] | CarryOut LEDR[8] | Overflow LEDR[9] |
---|---|---|---|---|---|---|---|---|

00 (Add) | 0101 | 1100 | ||||||

00 (Add) | 1111 | 0101 | ||||||

00 (Add) | 1010 | 0011 | ||||||

00 (Add) | 1101 | 1010 | ||||||

01 (Sub) | 0101 | 1100 | ||||||

01 (Sub) | 1111 | 0101 | ||||||

01 (Sub) | 1010 | 0011 | ||||||

01 (Sub) | 1101 | 1010 | ||||||

10 (And) | 0101 | 1100 | ||||||

10 (And) | 1111 | 0101 | ||||||

10 (And) | 1010 | 0011 | ||||||

10 (And) | 1101 | 1010 | ||||||

11 (Xor) | 0101 | 1100 | ||||||

11 (Xor) | 1111 | 0101 | ||||||

11 (Xor) | 1010 | 0011 | ||||||

11 (Xor) | 1101 | 1010 |

Record the results in the table, and use the calculator to check with your results (correct or not).