**Lesson 03: Verilog Modeling Styles**

## Dataflow Modeling

**Dataflow Modeling**

Dataflow modeling provides the means of describing a combinational circuit by their boolean expression rather than by their gate circuit. Dataflow modeling uses a number of operators that act on operands to produce the desired logic circuits. Verilog HDL provides different types of operators that act as operands. Some of the operators are described below:

**Table 1**: Verilog HDL Operators for Dataflow Modeling

Symbol | Operation |
---|---|

[] | bit-select or part-select |

() | parenthesis |

! | logical NOT |

&& | logical AND |

|| | logical OR |

~ | bit-wise not |

& | bit-wise and |

| | bit-wise or |

~& | bitwise nand |

>~| | bit-wise nor |

^ | bit-wise xor |

~^ or ^~ | bit-wise xnor |

+ / - | unary (sign) plus / minus |

{} | concatenation |

{{}} | replication |

Symbol | Operation |
---|---|

+ | binary arithmetic addition |

- | binary arithmetic subtraction |

>* | binary arithmetic multiply |

/ | binary arithmetic divide |

>% | binary arithmetic modulus |

<< | shift left |

>> | shift right |

<<< | Arithmetic shift left |

>>> | Arithmetic shift right |

== | equality |

!= | inequality |

> | greater than |

< | less than |

>= | greater than or equal to |

<= | less than or equal to |

? : | conditional |

Dataflow modeling uses continuous assignments and the keyword **assign**. A continuous assignment is a statement that assigns a value to a net. The datatype net is used in Verilog HDL to represent a physical connection between circuit elements. The value assigned to the net is specified by an expression that uses operands and operators. As an example, assuming that the variables were declared, a 2-to-1 multiplexer with data inputs A and B, select input S, and output Y is described with the continuous assignment:

**assign** Y=(A&S)|(B&S);