KB 02: Synthesizable Coding of Verilog

The synthesis is to convert the description language into a circuit that can be implemented in hardware. However, most Verilog courses do not tell us whether you have to consider that the code is synthesizable or not, while you use Verilog to design the system.

When you use Verilog to describe your circuit, keep in mind the following:

  1. Do not use the initialization block.
  2. Do not use delay statements.
  3. Do not use statements with uncertain loop times, such as: forever, while, etc.
  4. Use synchronous methods to design the circuit as possible.
  5. Use behavioral modeling to design the circuit as possible.
  6. When using an always block describes the combinational circuit, all the inputs should be listed in the sensitivity list.
  7. All the User-Defined Primitives (UDP) are not synthesizable.
  8. The repeat, wait, fork/join, deassign, event, force/release statements are not supported by synthesis tools.
  9. Hierarchical references of registers and nets inside the modules are not supported.
    module my_module;
        assign my_net = top.my_module1.my_net;
    endmodule