KB01: Verilog FAQ
Can I use always statements to model combinational logic? How?
Ideally, concurrent statements are used to model combinational logic, and always statements are used to model sequential logic (flip flops and latches). However, always statements are not restricted to that. You can model combinational logic using them. But it is important to note that when using an always statement to make a combinational logic, the sensitivity list of the always statement should contain all the signals which are being 'read' in that always block. In other words, to synthesize combinational logic using an always block, all inputs must appear in the sensitivity list.
For example, if you were to model a mux, you would say:
Using an always statement to model combinational logic is handy because statements like if, case, etc (which are very useful and intuitive) can only be written inside always statements.
The Rules for Sequential Logic Design
Synchronous Sequential Logic Design: Using Flip-Flops
There are two important things you should know when you design synchronous sequential logic:
- The sensitivity list of the always statement must have a clock signal (or a reset signal, if it is an asynchronous reset). And it should be either 'posedge' or 'negedge' in the sensitivity list before the clk. This is because flip-flops are edge-triggered elements
- Using non-blocking assignments in the always block.
Flip-flop without a reset (Flip-flop is edge-triggered element)
Flip-flop with an Async reset
Flip-flop with a Sync reset
Sequential Logic Design: Using Latches
Resettable latch (Latch is a level triggered element)