1-Wire Communication

The basis of 1-Wire technology is a serial protocol using a single data line plus ground reference for communication. 1-Wire protocol uses CMOS/TTL logic and operates at a supply voltage ranging from 2.8V to 6V.

Overview of the 1-Wire BUS

1-Wire provides low-speed data, signaling, and power over a single conductor. It is similar in concept to I2C


There are two types of 1-Wire protocol:

  • Dallas 1-Wire Protocl
  • MaxDetect 1-Wire Protocol

Inter-Integrated Circuit Bus (I2C Bus)

 I2C bus logo

I2C (Inter-Integrated Circuit), pronounced I-squared-C, is also called IIC (pronounced I-I-C), or I2C (pronounced I-two-C). The I2C was designed by Philips in the early '80s, and It is typically used for lower-speed communication between peripheral devices and microcontrollers in short-distance. For example, EEPROM, ADC, and RTC etc.

I2C is a multi-master and multi-slave serial communication protocol means that we have the freedom to attach multiple IC at a time with the same bus. In I2C protocol, communication always started by the master and in the case of multi-master, only one master has the ownership of the bus.

 

I2C Physical Layer

I2C is basically two-wire communication protocol. It uses only two wire for the communication. In which one wire is used for the data (SDA) and other wire is used for the clock (SCL). In I2C, both buses are bidirectional, which means master able to send and receive the data from the slave. The clock bus is controlled by the masters, but in some situations slave devices may force the clock low at times to delay the master sending more data, or to require more time to prepare data before the master attempts to clock it out. This is called "Clock Stretching" and is described on the protocol part.

All slave and master are connected with same data and clock bus, here important thing is to remember these buses are connected to each other using the WIRE-AND configuration which is done by to putting both pins is "open drain". Open drain means that device can pull the corresponding signal line low, but cannot drive it high. Thus, the open-drain configuration allows in I2C to connect multiple nodes to the bus without any short circuits from signal contention.

In the other word, the open-drain allows the master and slave to drive the line low and "release" to high impedance state. In that situation, when master and slave release the bus, need a pull-up resistor to pull the line high. Each signal line has a pull-up resistor on it, to restore the signal to high when no device is asserting it low. The value of the pull-up resistor is very important as per the perspective of the design of I2C system because the incorrect value of pull-up resistor can lead to signal loss. But a good rule of thumb is to start with 4.7 KΩ and adjust down if necessary.

I2C Fig1
Figure 1: Basic Internal Structure of the Slave and Master Devices

Figure 1 shows a simplified view of the internal structure of the slave and master devices on the SDA/SCL lines, consisting of a buffer to read input data, and a pull-down FET to transmit the data. A device is only able to pull the bus line low (provide short to ground) or release the bus line (high impedance to ground) and allow the external pull-up resistor to raise the voltage. This is an important concept to realize when dealing with I2C devices, since no device may hold the bus high. This property is what allows bidirectional communication to take place.

I2C is a fairly robust protocol, and can be used with short runs of wire (2 ~ 3 m). For long runs, or systems with lots of devices, smaller resistors are better.

Wired Connection

i2c connection s

The above diagram shows a simplified equivalent circuit for an I2C connection between the masters and slaves. All I2C master and slave devices are connected with only two wires: serial data (SDA) and serial clock (SCL). Each device can be a transmitter, a receiver or both. Some devices are masters – they generate bus clock and initiate communication on the bus, other devices are slaves and respond to the commands on the bus. In order to communicate with specific device, each slave device must have an address which is unique on the bus. I2C master devices (usually microcontrollers) don't need an address since no other (slave) device sends commands to the master.

We know that I2C communication protocol supports the multiple masters and multiple slaves, but most system designs include only one master.

Bus Signals

The I2C uses two signals: SDA and SCL. Both signals are bidirectional, and connected via resistors to a positive power supply voltage. All the devices on the bus must use open-collector or open-drain pins. Therefore, when the bus is free, both signals are logic high. Activating the signal means pulling it down (wired AND) to logic 0. The number of the devices on a single I2C bus is almost unlimited  — the only requirement is that the bus capacitance does not exceed 400 pF.

Signal Timing

The I2C is a serial synchronous communication protocol. Each clock just transfers one bit of data. The SDA signal can only be changed when the SCL signal is low, this means the data should be stable when the clock is high.

BitTransferOnTheI2c Bus s

I2C Data Transfer Protocol

I2CDataTransferProtocol s

Data on the I2C bus is transferred in 8-bits. There are no limitation on the number of bytes, however, each byte must be followed by an acknowledge (ACK) bit. This bit signals whether the device is ready to proceed with the next byte. For all data bits including the ACKnowledge bit, the master must generate clock pulses. If the slave device does not acknowledges transfer, this means that there is no more data or the device is not ready for the transfer yet. The master device must either generate a STOP or REpeated START condition bit.

START CONDITION

The default state of SDA and SCL line is high. A master issuing the Start condition first pulls the SDA line low, and next pulls the SCL line low. This puts all slave devices on notice that a transmission is about to start. The I2C bus is considered busy after the assertion of the START bit. If two master devices wish to take ownership of the bus at one time, whichever device pulls SDA low first wins the race and gains control of the bus.

I2C StartCondition s

STOP CONDITION

Once all the data frames have been sent, the master will generate a stop condition. The bus master first releases the SCL and then the SDA line. The I2C bus is considered free after the assertion of the STOP bit.

I2C StopCondition s

A Stop condition ALWAYS denotes the END of a transmission. Even if it is issued in the middle of a transaction or in the middle of a byte. It is "good behavior" for a master that, in this case, it disregards the information sent and resumes the "listening state", waiting for a new start condition.

REPEATED START

The repeated start condition similar to the START condition but both are different to each other. The repeated start is asserted by the master before the stop condition (When the bus is not in an idle state).

A Repeated Start condition is asserted by the master when bus master does not want to lose their control from the bus. The repeated start is beneficial for the master when it wants to start a new communication without the asserting the stop condition.

I2C ReStartCondition s

Repeated start is beneficial when more than one master connected with the I2c Bus.

CLOCK STRETCHING

Sometimes, the master data rate will exceed the slave's ability to provide data. The slave is not ready to sent the data, for example, the A/D conversion has not been completed, or the previous operation has not been completed.

In this case, the slave device will execute what is referred to as "clock stretching". Typically, all clocking is driven by the bus master. The slave simply places the data on the bus or fetches data off the bus in response to the master's clock pulse. At any time during the data transfer processing, an addressed slave can pull the SCL line low to pause the transaction. After the processing of the received data, slave will release the SCL line high to resume the communication.

The clock stretching is the way in which slave drive the SCL line but it is the fact, most of the slave do not drive the SCL line

I2C ClockStretching s

In I2c communication protocol, most of the I2C slave devices do not use the clock stretching feature, but every master should support the clock stretching.

Arbitration in I2C

The arbitration is required in case of multi-master, where more than one master is tried to communicate with a slave simultaneously. In I2C arbitration is achieved by the SDA line.

For example, if two masters in the I2C bus are tried to communication with a slave simultaneously, then they will assert a START condition on the bus. The SCL clock line would be already synchronized by the wired and logic.

I2C Arbitration s

In the above case, everything will be good till the state of SDA line will same what is the masters driving on the bus. If any master sees that the state of SDA line differs, what is it driving then they will exit from the communication and lose their arbitration.

Master which is losing their arbitration will wait till bus become free.

 

Handshaking Process in I2C Protocol

Communication with 7-bit I2C Slave Address

CommWith7bitI2cAddr s

Each slave device on the I2C bus should have an unique 7-bit address, called slave address. The master device generates all the serial clock pules and the START and STOP conditions bit. Data is transferred with the most significant bit (MSb) first.

Data transfer from a master transmitter to a slave receiver (data write mode)

i2c write s

  1. Before transmitting, the master needs to detect the bus status. If the bus is not busy, this means both data and clock lines remain high, then the master sends a START condition bit.
  2. The first byte transmitted by the master is the 7-bit address of the slave (it wishes to communicate with) and followed by a direction bit representing whether it wishes to write (0) to or read (1) from the slave.
  3. If the salve exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address.
  4. When the master receives the ACK bit, it will transmit the next data on the bus and waiting for ACK signal from the slave. Continue this step until all the data are transmitted.
  5. The master ends transmission with a STOP bit.

Data transfer from a slave transmitter to a master receiver (data read mode)

i2c read s

  1. Before transmitting, the master needs to detect the bus status. If the bus is not busy, this means both data and clock lines remain high, then the master sends a START condition bit.
  2. The first byte (salve address with a read bit) is transmitted by the master.
  3. The slave then returns an ACK bit with the first data byte tranmitted to the master.
  4. The master returns an ACK bit, then slave continuous sends the next data on the bus. The master sends an ACK bit after every byte except the last one.
  5. When the master receives the last data byte, a NAC (not acknowledge) bit will be sent to the slave.
  6. The master ends transmission with a STOP bit.

Combined Mode

CombinedI2cComm s

Sometimes the master needs to write some data and then read from the slave device. In such cases it must first write to the slave device, change the data transfer direction and then read from the slave device. This means sending the I2C address with the R/W bit set to write and then sending some additional data like register address. After writing is finished, the master device generates REpeated START (RESTART) condition and sends the I2C address with the R/W bit set to read. After this, the data transfer direction is changed and the master device starts reading the data.

7-bit I2C Slave Address

Two slave addressing formats are defined in the I2C specification: 7-bit and 10-bit addressing. Standard Mode I2C makes use of 7-bit addressing. 10-bit addressing was later added as an extension to standard mode I2C.

In 7-bit addressing format, the slave address is transferred in the first byte after the START condition bit. The bit[7:1] of the byte comprise the slave address, followed by a direction bit at bit[0]. The format is shown as the following diagram. 

 

7 bit addressing format s

A seven bit wide address space theoretically allows 128 I2C addresses – however, some addresses are reserved for special purposes. Thus, only 112 addresses are available with the 7 bit address format.

Reserved address in 7-bit address space

Two groups of addresses are reserved for special functions:

  • 000 0XXX
  • 111 1XXX

The following table shows I2C addresses reserved for special purposes:

  Slave Address R/W bit Description
1  000 0000 General call address
2 000 0000 1 START byte
3 000 0001 X CBUS address
4 000 0010 X Reserved for different bus format
5 000 0011 X Reserved for feture purposes
6 000 01XX X Hi-Speed Master code
7 111 10XX X 10-bit slave addressing format
8 111 11XX 1 Device ID

10-bit I2C Slave Address

10-bit addressing expands the number of possible addresses. Devices with 7-bit and 10-bit addresses can be connected to the same I2C-bus, and both 7-bit and 10-bit addressing can be used in all bus speed modes. Currently, 10-bit addressing is not being widely used.

10 bit addressing format s

 

10 bit address writing s10 bit address writing reading s

 

Feature of I2C Bus

  • Synchronous communication using two bidirectional open-drain lines pulled up with resistors
    1. Serial Data Line (SDA)
    2. Serial Click Line (SCL)
  • Typical voltages used: +5 V or +3.3 V
  • Can be designed as
    • a single master and multiple slaves
    • multiple masters
    • a combination of masters and slaves
  • Each device connected to the I2C bus is software-addressable by an unique address
  • Bus speed supported:
    • Low-speed mode: 10 Kbps
    • Standard-mode: 100 Kbps
    • Fast-mode: 400 Kbps
    • Fast-mode Plus: 1 Mbps
    • High-speed Mode: 3.4 Mbps

References:

Serial Peripheral Interface Bus (SPI)

The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.The SPI bus is commonly used for communication with flash memory, sensors, real-time clock (RTCs), analog-to-digital converters, and mode.

 

Interface and Features

SPI features include:

  • SPI signals include:
    • SCLK: Serial Clock (output from master)
    • MOSI: Master Output Slave Input (data output from master)
    • MISO: Master Input Slave Output (data output from slave)
    • /SS: Slave Select (often active low, output from master)
    • SDAT: Serial Data I/O (bidirection I/O, combined MOSI and MISO signals together)
  • Data length: 3- to 16-bit data width
  • Bit rate: support up to 18 Mbps
  • SPI serial bus can be configured as 4-wire (default) and 3-wire mode

SPI Operating Modes

There is no pre-defined protocol in SPI, the master and slave need to agree about the data frame for the exchange. The data frame is described by two parameters: clock polarity (CPOL) and clock phase (CPHA). CPOL parameter is used to define whether the clock is idle when high or low. CPHA parameter is used to shift the sampling phase. If CPHA = 0 the data are sampled on the leading (first) clock edge. If CPHA = 1 the data are sampled on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. The 4 modes combine polarity and phase according to following table:

Table: SPI Clock Phase (CPHA) and Clock Polarity (CPOL) Operation

Mode Clock Polarity
(CPOL)
Clock Phase
(CPHA)
SCLK Transmit Edge SCLK Receive Edge SCLK Idle State
0 0 0 Falling Rising Low
1 0 1 Rising Falling Low
2 1 0 Rising Falling High
3 1 1 Falling Rising High

CPOL: used for clock idle state

  • 0 — Clock idle low level
  • 1 — Clock idle high level

CPHA: used to shift the sampling phase

  • 0 —  Data Sampled at the leading edge (no delay)
  • 1 —  Data Sampled at the trailing edge (delay)

Timing Diagram for Clock Polarity and Phase

The following diagram shows the four possible states for these parameters and the corresponding mode in SPI.

SPI Modes

  • Mode 0 — CPOL = 0, CHPA = 0
    SPI Mode0 s
    Data is sampled at the leading rising edge of the clock. The data must be avaliable before the first clock signal rising. The clock idle state is low (0). The data on MOSI ad MISO lines must be stable while the clock is high, and can be change when the clock is low. The data is captured on the clock's rising transition and propagated on falling clock transition. Mode 0 is by far the most common mode for SPI bus slave communication.
  • Mode 1 — CPOL = 0, CHPA = 1
    SPI Mode0 s
    Data is sampled at the trailing falling edge of the clock. The first clock signal rising can be used to prepare the data. The clock idle state is low (0). The data on MOSI and MISO line must be stable while the clock is low and can be changed when the clock is high. The data is captured on the clock's falling tranaction abd propagated on rising clock transaction.
  • Mode 2 — CPOL = 1, CHPA = 0
    SPI Mode0 s
    Data is sampled at the leading falling edge of the clock. The data must be available before the first clock signal falling. The clock idle state is high (1). The data on MOSI and MISO lines must be stable while the clock is low and can be changed when the clock is high. The data is captured on the clock's falling transition and propagated on rising clock transition.
  • Mode 3 — CPOL = 1, CHPA = 1
    SPI Mode0 s
    Data is sampled at the trailing rising edge of the clock. The first clock signal falling can be used to prepare the data. The clock idle state is one. The data on MISO and MOSI lines must be stable while the clock is high and can be changed when the clock is low. The data is captured on the clock's rising transition and propagated on falling clock transition.

 

SPI Bus Connection Modes

SPI bus connection can be configured on 4-wire or 3-wire mode.

  • 4-wire serial bus mode: SCLKMOSIMISO, AND SS signals

SPI 4WireMode s

  • 3-wire serial bus mode: SCLKSDAT, and SS signals

SPI 3WireMode s

4-wire bus mode is SPI standard connection mode. It supports full-duplex data transaction, which means SPI allows to transmit and receive data simultaneously on two data lines (MOSI and MISO),

In 3-wire serial bus mode, MOSI abd MISO lines are combined to a single bidirectional data line (SDAT). Transaction are half-duplex to allow for bidirectional communication. Reducing the number of data lines and operating in half-duplex mode also decreases maximum possible throughput; many 3-wire devices have low performance requirements and are instead designed with low pin count in mind.

 

SPI Connections for Multiple Slaves

SPI devices communicate in full duplex mode using a master-slave architecture with a signal master. There are two ways to connect multiple slaves with a master:

Individual Slave Select Configuration

In this configuration, the SCLK, MOSI and MISO are shared by all devices. Each device has an individual slave select (/SS) lines. The master will pull low on a slave /SS line to select a device for communication. A pull-up resistor on the /SS line is highly recommended for each individual device to reduce cross-talk between devices. The data lines (MOSI and MISO) are connected with slaves in parallel connection.

SSI Connection01

Daisy Chain Configuration

SPI devices may be connected in a daisy chain configuration. The data lines (MOSI and MISO) are coonected with slaves in serial connection — the first slave data output being connected to the second slave data input, etc. The whole chain acts as a communication shift register; daily chaining is often done with shift registers to provide a block of inputs or outputs through SPI. This configuration only requires a single /SS line from the master, rather than a separate /SS line for each slave.

SSI Connection02

 

To write code for a new SPI device, you need to note a few things:

  • What is the maximum SPI clock speed the device can use?
  • Is data shifted in Most Significant bit (MSb) or Least Significant bit (LSb) first?
  • Is the data clock idle when high or low? Are samples on the rising or falling edge of clock pulses?
  • Is the connection in 4-Wire or 3-Wire mode?

 

 Reference:

Pulse-Width Modulation (PWM)

 

Pulse-Width Modulation — What is it?

The good definition of Pulse-Width Modulation (PWM) is already in the name itself. It means modulating/varying the width of the pulse only, not the frequency. In the digital control system, PWM is used to control the amount of power sent to a device. Therefore, the PWM is a very effective technique for controlling analog devices using the digital outputs of microcontroller. It is widely used in many fields, such as measurement, communication, power control and transformation.

Principle

A PWM signal consists of two main components that define its behavior: a duty cycle and a frequency.

DutyCycle s

  • Duty Cycle
    The duty cycle describes the amount of time the signal is in a high (on) state as a percentage of the total time of it takes to complete one cycle. A lower duty cycle corresponds to lower power, because the power is off for most of the time. Duty cycle is expressed percent, 100% duty cycle would be fully on as same as setting the signal to Vcc (high); 0% duty cycle would be the same as grounding the signal.
  • Frequency
    The frequency determines how fast the PWM completes a cycle, ie. 100Hz would be 100 cycles per second. Another words, it shows how fast the PWM switches between high and low states.

In the digital system, PWM is the method to produce variable voltage using digital means. Typically, digital system only has two output voltages, the high (5V, 3.3V … etc.) or low (0V). But, how it is possible that digital system can produce a voltage that is between the high and low voltages? Here, we use mathematic to analyze the PWM signal and the average output.

Mathematical Analysis of PWM signal

PWM uses a rectangular pulse wave whose pulse width is modulated resulting in the variation of the average value of the waveform. Consider a waveform such as shown in figure 2.

PWMSignal sFigure 2: A Pulse Wave

The pulse signal is f(t) with period T and a duty cycle D (0.0~1.0). The average voltage of the waveform is given by:

\bar y = \frac{1}{T}\int_0^T {f(t)dt}

Just focus on one cycle T, as f(t) is a pulse wave, its positive pulse is for 0 < t < D×T and zero pulse is for D×T < t < T. The above expression then becomes:

\begin{array}{l}
\bar y = \frac{1}{T}\left( {\int_0^{DT} {1\;dt}  + \int_{DT}^T {0\;dt} } \right)\\
\quad  = \frac{1}{T}\left[ {DT \times 1 + T(1 - D) \times 0} \right]\\
\quad  = D
\end{array}

From this, it is obvious that the average value of the signal is directly dependent on the duty cycle D.

For example, if a digital signal produces pulse high (5V) and low (0V) equally, let us assume the signal in high state for 1 microsecond and in low state for 1 microsecond. The duty cycle is 50%, so the average voltage would be 2.5 volts. Now, change the high voltage in high state for 7 microseconds and in low state for 3 microseconds. The duty cycle now is became to 70%, the average voltage would measure 70% of 5 volts, or 5v x 0.7 = 3.5 volts.


Types of PWM

There are a couple types of PWM, and it can be classified in different ways.

Classify PWM Signal by Methods: Symmetric and Asymmetric

There are two kinds of PWM signals: Symmetric and Asymmetric.

  1. Symmetric PWM:
    • The pulses of a symmetric PWM signal are always symmetric with respect to the center of each PWM period.
    • Symmetric PWM are often used for three-phase AC induction and brushless DC motors, due to the lower harmonic distortion that is generated on phase currents in comparsion to asymmetric PWM methods.
  2. Asymmetric PWM:
    • The pulses of an asymmetric PWM signal always have the same side aligned with one end of each PWM period.
    • Asymmetric PWM can be used for stepper motors and other variable-reluctance motors.

SymmetricAsymmetricPWM s
Figure 3: Three Types of PWM Signal: Center-Aligned, Left-Aligned, and Right-Aligned PWMs

Classify PWM Signal by Signal-Alignment

The PWM signal can be classified by signal-alignment in four different types:

  1. Center-aligned PWM:
    • Symmetric PWM
    • Center-aligned PWMs are most often used in AC motor control to maintain phase alignment
  2. Left-aligned PWM
    • Asymmetric PWM
    • Left-aligned PWMs are used for most general-purpose PWM uses
  3. Right-aligned PWM
    • Asymmetric PWM
    • Right-aligned PWMs are typically only used in special cases that require alignment opposite of left-aligned PWMs
  4. Dual-edge PWM
    • Dual-edged PWMs are optimized for power conversion where phase alignment must be adjusted

 


Generating PWM with Microcontroller using Timer/Counter

The basic idea to generate PWM signal is using a counter (or timer), a CMP (compare) value, and a digital output pin. The counter continuously counts to up or down, and is compared with CMP value. The digital output (PWM) will be changed when the counter matches the CMP value, or when counter resets. It can be implemented by software or hardware. Most of microcontrollers already have hardware modules that can generate PWM signal after initialize the registers.

PWMGenertor 1 s

PWM Timer

The PWM timer in the microcontroller runs in one of two modes: Count-Down mode or Count-Up/Down mode.

  • In Count-Down mode, the timer counts from the Period (LOAD) value to zero, goes back to the Period (LOAD) value, and continues counting down.
  • In Count-Up/Dow mode, the timer counts from zero up to the Period (LOAD) value, back down to zer, back up to the Period (LOAD) value, and so on.

Generally, Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals.

Check the microcontroller's datasheet about PWM timer. Most of ARM microcontrollers use Count-Down mode.

Reference:

https://electronics.stackexchange.com/questions/34444/how-to-generate-a-pwm-signal-that-varies-atleast-20times-between-0-5v-range-usin

 

Universal Asynchronous Receiver-Transmitter (UART)

 

A Universal Asynchronous Receiver/Transmitter, abbreviated UART (pronounced ' you-art '), is an asynchronous serial communication protocol. The universal designation indicates that the data format and transmission speeds are configurable. UART is very useful interface which can transmit signals without needing to synchronize with a clock signal. This method of transmission is extremely useful for reducing wires and I/O pins compared to parallel systems which transmit data faster bus are far more complex. It provides a cost effective simple and reliable communication between one controller to another controller or between a controller and host computer.

In the UART system, the parallel data is reformatted into a serial stream, and then sends it out through the transmitting wire. In a simplest connection form, a UART can be thought of as a two wire communication system where one line is transmitting and the other is receiving. UART can be configured for Full Duplex, Half Duplex, RX only, or TX only version.

UARTs are commonly used in conjunction with communication standard such as RS-232 or RS-485. The voltage levels of RS-232 are -12V and +12V. Usually all the digital systems work on TTL or CMOS voltage levels, which cannot directly compatible with those of RS-232, a level transition buffer such as MAX232 must be used.

Data Packet Format

UART transmitted data is organized into packets. Each packet contain [1 START bit ] + [ DATA frame (5 ~ 9 bits) ] + [ PARITY bit (optional) ] + [ STOP bit (1, 2) ], as shown in the following diagram.

UartProtocolFormat s

  • START bit
    In the Idle mode, the UART data line is held at high voltage level (logic 1). To start data transmission, the transmitting UART pulls the transmission line to low for one clock cycle. When the receiving UART detects the data line from high to low voltage transition, it begins reading the bits in the data frame at the frequency of the baud rate.
  • DATA frame
    The data frame contains the data being transferred. Options are 5, 6, 7, 8 (default), or 9. If the PARITY bit is not used, the length of the data frame could be up to 9-bits; if a parity bit is used, the maximum length of the data frame is up to 8-bits.
  • PARITY bit
    The parity bit is for error checking when the receiving UART receives a packet. This can be set to None (default), Odd, Even, or Mark/Space. If the data frame is 9-bits, then the Parity type must be Mark/Space. Parity bit is optional and it is actually not that widely used.
  • STOP bits
    To signal the end of the data packet, the sending UART drives the data transmission line from a low voltage to a high voltage. The STOP bit can be set to 1 (default) or 2 bits.

Baud Rate

The baud rate specifies how fast data is sent over a serial line. The units of the baud rate are bit-per-second (bps). The higher a baud rate goes, the faster data is sent and received, but the speed of data transfer is limited. Since there is no clock signal in the UART communication, the higher transmitting speed will easy leading to get errors on the receiving end. Therefore, each of the two UARTs must be communicating using a known baud rate, or bit frequency. The receiver and transmitter clock rates must be within 5% to avoid errors.

There are different sets of standard baud dates in used depending on the application. Usually the baud rates use 1200, 2400, 4800, 9600,19200, 38400, 57600 and 115200 bps. Both the local and remote UARTs must be configured for the same baud rate.

How UART Works?

UARTs transmit data asynchronously, which means there is no clock signal to synchronize the data bits from the transmitting UART to the receiving UART. Typically, an asynchronous communication needs handshaking signals to ensure sender and receiver to coordinate data transfers. In the UART, there are no extra handshaking signals between the transmitter and receiver. The transmitter generates a bit stream based on its clock signal, and then the receiver's goal is to use its internal clock signal to sample the incoming data. Therefore, the transmitter and receiver both need to have same transfer speed and data packet format. Then, the receiver's UART resynchronize the internal clocks on the falling edge of the start bit,and then read the center of each expected data bit based on the baud rate that is set.

UART Flow Control

UART Flow Control is a method for slow and fast devices to communicate with each other over UART without the risk of losing data.

Consider the case where two units are communicating over UART. A transmitter T is sending a long stream of bytes to a receiver R. R is a slower device than T, and at some point R cannot keep up. It needs to either do some processing on the data or empty some buffers before it can keep receiving data.

R needs to tell T to stop transmitting for a while. This is where flow control comes in. Flow control provides extra signaling to inform the transmitter that it should stop (pause) or start (resume) the transmission.

Several forms of flow control exist. For example, hardware flow control uses extra wires, where the logic level on these wires define whether the transmitter should keep sending data or stop. With software flow control, special characters are sent over the normal data lines to start or stop the transmission.

Hardware Flow Control: also called RTS/CTS Flow Control

When hardware flow control is enabled, two extra wires are needed in addition to the data lines. They are called RTS (Request to Send) and CTS (Clear to Send). The CTS signal is an input to the UART that is set by the other UART in the system when it is OK to send data on the bus. The RTS signal is an output of the UART informing the other UART on the bus that it is ready to receive data. The RTS line of one UART is connected to the CTS line of the other UART and vice versa. These lines are only valid before a transmission is started. If the signal is set or cleared after a transfer is started the change will only affect the next transfer.

HwFlowControl
Figure 2: The Connection for Hardware Flow Control

Software Flow Control

Software flow control does not use extra wires. Only 3 wires are required (RX, TX, and GND). Transmission is started and stopped by sending special flow control characters. The flow control characters are sent over the normal TX and RX lines. The flow control charac-ters are typically the ASCII codes XON and XOFF (0x11 and 0x13). If device A sends XOFF to device B it means that B should halt transmission to A until B receives an XON character from A.

SwFlowControl
Figure 3: The Connection for Software Flow Control

UART Configurations

Both UART communicating devices must operate at the same baud rate and have same configuration for successful communication:

  • Baud Rate
    • Standard Mode: 110 to 115,200 bps
    • Fast Mode: 230,400 ~ 921,600 bps, up to 4 Mbps
  • Modes: Full duples, half duplex, TX only, RX only
  • Data Bits: 5 ~ 9 bits
  • Endianess: Some UART devices offer the option to send the data in either LSb or MSb. The UART is almost always LSb.
  • Parity Types: None, Even, Odd, Mark/Space
  • Stop Bits: 1 or 2
  • Flow Control: None, Hardware (CTS/RTS), Software (Xon/Xoff)

The most common configuration for UART is often listed as "8N1", which is shorthand for eight data bits, no parity, and one stop bit. This is the default configuration for the UART communication protocol. Therefore, in most of applications you only need to set the baud rate.

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