UART Initialization & Configuration

The following steps show how to initialize PWM peripheral.

  1.  Enable Clock to the UART Modules (RCGCUART register)
    The first step to configure UART is to control the clocking for the UART modules. When enabled. an UART module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
    • 0: UART module is disabled
    • 1: Enable and provide a clock to UART module in RUN mode

    8 4 2 1   8 4 2 1  
    7 6 5 4   3 2 1 0 bit
    RCGCUART UART
    Module 7
    UART
    Module 6
    UART
    Module 5
    UART
    Module 4
    UART
    Module 3
    UART
    Module 2
    UART
    Module 1
    UART
    Module 0
    UART
    -  
    SYSCTL->RCGCUART =  MyDefines.h
                                        =  binary =  hex

    After enable clock signal, check the PRUART register until the corresponding bit set to 1.
    In C:
    while ( (SYSCTL->PRUART & (____) ) != (____ )) {};

  2. UART Control Register

    The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register:
    1. Disable the UART.
    2. Wait for the end of transmission or reception of the current character.
    3. Flush the transmit FIFO by cleraing bit 4 (FEN) in the UARTLCRH register.
    4. Reporogram the UARTCTL register.
    5. Enable the UART

    Bit/Field Name Value Description
    15 CTSEN Enable CTS (Clear To Send)
    0 CTS hardware flow control is disabled
    1 CTS hardware flow control is enabled
    14 RTSEN Enable RTS (Request To Send)
    0 RTS hardware flow control is disabled
    1 RTS hardware flow control is enabled
    11 RTS The status of RTS signal (If RTSEN is set, this bit is ignored)
    9 RXE UART RX (Receive) Enabele
    0 The RX is disabled
    1 The RX is enabled
    8 TXE UART TX (Transmit) Enable
    0 The TX is disabled
    1 The TX is enabled
    7 LBE UART Loop Back Enable
    0 Normal operation.
    1 The UnTX path is fed through the UnRX path.
    5 HSE High-Speed Enable
    0 The UART is clocking using the system clock divided by 16
    1 The UART is clocking using the system clock divided by 8
    Bit/Field Name Value Description
    4 EOT End of Transmission. This bit determines the behavior of the TXRIS bit in the UARTRIS register
    0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met
    1 The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer
    3 SMART ISO 7816 Smart Card Support
    0 Normal operation
    1 The UART operates in Smart Card mode
    2 SIRLP UART SIR Low-Power Mode
    0 Low-level bits are transmitted as an active High pulse with width of 3/16th of the bit period
    1 The UART operates in SIR Low-Power mode.
    1 SIREN UART SIR Enable
    0 Normal operation
    1 The IrDA SIR block is enabled.
    0 UARTEN UART Enable
    0 The UART is disabled.
    1 The UART is enabled.

    8 4 2 1   8 4 2 1   8 4 2 1   8 4 2 1  
    15 14 13 12 11 10 9 8 7 6 5 4   3 2 1 0 bit
    UARTCTL CTSEN RTSEN RTS RXE TXE  LBE HSE EOT  SMART SIRLP SIREN UARTEN
    0 0 - 0 - 0 -  

    UART->CTL =  MyDefines.h
              =  binary |=  hex

  3. Baud-Rate Divisor (BRD)
    A baud-rate divisor is a 22-bit number consisting of a 16-bit integer (UARTIBRD) and a 6-bit fractional part (UARTFBRD).

    The UARTLCRH register, the UARTIBRD and UARTFBRD registers are connected to an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed. So, any changes to the baud-rate divisor (UARTIBRD and/or UARTFBRD) must be followed by a write to the UARTLCRH register for the changes to take effect.


    There are four possible sequences to update the baud-rate registers:
    • UARTIBRD write, UARTFBRD write, and UARTLCRH write
    • UARTFBRD write, UARTIBRD write, and UARTLCRH write
    • UARTIBRD write and UARTLCRH write
    • UARTFBRD write and UARTLCRH write

    31 ~ 16 15 ~ 0 bit
    UARTIBRD DIVINT UART
    0  
    UART->IBRD =  decimal
    31 ~ 4 5 ~ 0 bit
    UARTFBRD DIVFRAC UART
    0  
    UART->FBRD =  decimal

  4. UART Line Control, High Byte (UARTLCRH)
    The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register.
    8 4 2 1   8 4 2 1  
    7 6 5 4   3 2 1 0 bit
    UARTCTL  SPS WLEN FEN STP2 EPS PEN BRK
    -  
    UART->LCRH =  MyDefines.h
                  =  binary |=  hex

  5. Baud Clock Source for UART Module
    If the PIOSC is used for the UART baud clock, the system clock frequency must be at least 9 MHz in Run mode.